mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
synced 2025-12-23 17:55:05 +03:00
ad95189d09
Add clock, reset and stream-id header files and include them in the overlay dts. Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Change-Id: I1835cff21c34b143e58ead405af7f64bd9a6cb89 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2763002 Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
297 lines
11 KiB
C
297 lines
11 KiB
C
/*
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* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_OOT_H
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#define DT_BINDINGS_MEMORY_TEGRA234_MC_OOT_H
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/*
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* memory client IDs
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*/
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/* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */
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#define TEGRA234_MEMORY_CLIENT_PTCR 0x00
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/* MSS internal memqual MIU7 read clients */
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#define TEGRA234_MEMORY_CLIENT_MIU7R 0x01
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/* MSS internal memqual MIU7 write clients */
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#define TEGRA234_MEMORY_CLIENT_MIU7W 0x02
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/* MSS internal memqual MIU8 read clients */
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#define TEGRA234_MEMORY_CLIENT_MIU8R 0x03
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/* MSS internal memqual MIU8 write clients */
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#define TEGRA234_MEMORY_CLIENT_MIU8W 0x04
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/* MSS internal memqual MIU9 read clients */
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#define TEGRA234_MEMORY_CLIENT_MIU9R 0x05
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/* MSS internal memqual MIU9 write clients */
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#define TEGRA234_MEMORY_CLIENT_MIU9W 0x06
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/* MSS internal memqual MIU10 read clients */
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#define TEGRA234_MEMORY_CLIENT_MIU10R 0x07
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/* MSS internal memqual MIU10 write clients */
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#define TEGRA234_MEMORY_CLIENT_MIU10W 0x08
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/* MSS internal memqual MIU11 read clients */
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#define TEGRA234_MEMORY_CLIENT_MIU11R 0x09
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/* MSS internal memqual MIU11 write clients */
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#define TEGRA234_MEMORY_CLIENT_MIU11W 0x0a
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/* MSS internal memqual MIU12 read clients */
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#define TEGRA234_MEMORY_CLIENT_MIU12R 0x0b
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/* MSS internal memqual MIU12 write clients */
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#define TEGRA234_MEMORY_CLIENT_MIU12W 0x0c
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/* MSS internal memqual MIU13 read clients */
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#define TEGRA234_MEMORY_CLIENT_MIU13R 0x0d
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/* MSS internal memqual MIU13 write clients */
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#define TEGRA234_MEMORY_CLIENT_MIU13W 0x0e
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#define TEGRA234_MEMORY_CLIENT_NVL5RHP 0x13
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#define TEGRA234_MEMORY_CLIENT_NVL5R 0x14
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/* Host channel data read clients */
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#define TEGRA234_MEMORY_CLIENT_NVL5W 0x17
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#define TEGRA234_MEMORY_CLIENT_NVL6RHP 0x18
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#define TEGRA234_MEMORY_CLIENT_NVL6R 0x19
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#define TEGRA234_MEMORY_CLIENT_NVL6W 0x1a
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#define TEGRA234_MEMORY_CLIENT_NVL7RHP 0x1b
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#define TEGRA234_MEMORY_CLIENT_NVENCSRD 0x1c
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#define TEGRA234_MEMORY_CLIENT_NVL7R 0x1d
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#define TEGRA234_MEMORY_CLIENT_NVL7W 0x1e
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#define TEGRA234_MEMORY_CLIENT_NVL8RHP 0x20
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#define TEGRA234_MEMORY_CLIENT_NVL8R 0x21
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#define TEGRA234_MEMORY_CLIENT_NVL8W 0x22
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#define TEGRA234_MEMORY_CLIENT_NVL9RHP 0x23
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#define TEGRA234_MEMORY_CLIENT_NVL9R 0x24
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#define TEGRA234_MEMORY_CLIENT_NVL9W 0x25
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/* Reads from Cortex-A9 4 CPU cores via the L2 cache */
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#define TEGRA234_MEMORY_CLIENT_MPCORER 0x27
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#define TEGRA234_MEMORY_CLIENT_NVENCSWR 0x2b
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/* DLA0ARDB read clinets */
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#define TEGRA234_MEMORY_CLIENT_DLA0RDB 0x2c
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/* DLA0ARDB1 read clinets */
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#define TEGRA234_MEMORY_CLIENT_DLA0RDB1 0x2d
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/* DLA0 writes */
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#define TEGRA234_MEMORY_CLIENT_DLA0WDB 0x2e
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/* DLA1ARDB read clinets */
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#define TEGRA234_MEMORY_CLIENT_DLA1RDB 0x2f
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/* Writes from Cortex-A9 4 CPU cores via the L2 cache */
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#define TEGRA234_MEMORY_CLIENT_MPCOREW 0x39
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/* OFAA client */
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#define TEGRA234_MEMORY_CLIENT_OFAR1 0x3a
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/* ISP read client for Crossbar A */
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#define TEGRA234_MEMORY_CLIENT_ISPRA 0x44
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/* ISP read client 1 for Crossbar A */
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#define TEGRA234_MEMORY_CLIENT_ISPFALR 0x45
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/* ISP Write client for Crossbar A */
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#define TEGRA234_MEMORY_CLIENT_ISPWA 0x46
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/* ISP Write client Crossbar B */
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#define TEGRA234_MEMORY_CLIENT_ISPWB 0x47
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/* XUSB_HOST read clients */
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#define TEGRA234_MEMORY_CLIENT_XUSB_HOSTR 0x4a
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/* XUSB_HOST write clients */
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#define TEGRA234_MEMORY_CLIENT_XUSB_HOSTW 0x4b
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/* XUSB read clients */
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#define TEGRA234_MEMORY_CLIENT_XUSB_DEVR 0x4c
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/* XUSB_DEV write clients */
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#define TEGRA234_MEMORY_CLIENT_XUSB_DEVW 0x4d
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/* TSEC Memory Return Data Client Description */
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#define TEGRA234_MEMORY_CLIENT_TSECSRD 0x54
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/* TSEC Memory Write Client Description */
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#define TEGRA234_MEMORY_CLIENT_TSECSWR 0x55
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/* XSPI writes */
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#define TEGRA234_MEMORY_CLIENT_XSPI1W 0x56
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/* OFAA client */
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#define TEGRA234_MEMORY_CLIENT_OFAR 0x5d
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/* OFAA writes */
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#define TEGRA234_MEMORY_CLIENT_OFAW 0x5e
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/* sdmmca memory read client */
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#define TEGRA234_MEMORY_CLIENT_SDMMCRA 0x60
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/* sdmmca memory write client */
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#define TEGRA234_MEMORY_CLIENT_SDMMCWA 0x64
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/* SE Memory Return Data Client Description */
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#define TEGRA234_MEMORY_CLIENT_SEU1RD 0x68
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/* SE Memory Write Client Description */
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#define TEGRA234_MEMORY_CLIENT_SUE1WR 0x69
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/* DLA1ARDB1 read clinets */
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#define TEGRA234_MEMORY_CLIENT_DLA1RDB1 0x6e
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/* DLA1 writes */
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#define TEGRA234_MEMORY_CLIENT_DLA1WRB 0x6f
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/* VI FLACON read clinets */
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#define TEGRA234_MEMORY_CLIENT_VI2FALR 0x71
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/* VI Write client */
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#define TEGRA234_MEMORY_CLIENT_VI2W 0x70
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/* VI Write client */
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#define TEGRA234_MEMORY_CLIENT_VIW 0x72
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/* NISO display read client */
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#define TEGRA234_MEMORY_CLIENT_NVDISPNISOR 0x73
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/* NVDISPNISO writes */
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#define TEGRA234_MEMORY_CLIENT_NVDISPNISOW 0x74
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/* XSPI client */
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#define TEGRA234_MEMORY_CLIENT_XSPI0R 0x75
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/* XSPI writes */
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#define TEGRA234_MEMORY_CLIENT_XSPI0W 0x76
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/* XSPI client */
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#define TEGRA234_MEMORY_CLIENT_XSPI1R 0x77
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#define TEGRA234_MEMORY_CLIENT_NVDECSRD 0x78
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#define TEGRA234_MEMORY_CLIENT_NVDECSWR 0x79
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/* Audio Processing (APE) engine read clients */
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#define TEGRA234_MEMORY_CLIENT_APER 0x7a
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/* Audio Processing (APE) engine write clients */
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#define TEGRA234_MEMORY_CLIENT_APEW 0x7b
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/* VI2FAL writes */
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#define TEGRA234_MEMORY_CLIENT_VI2FALW 0x7c
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#define TEGRA234_MEMORY_CLIENT_NVJPGSRD 0x7e
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#define TEGRA234_MEMORY_CLIENT_NVJPGSWR 0x7f
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/* SE Memory Return Data Client Description */
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#define TEGRA234_MEMORY_CLIENT_SESRD 0x80
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/* SE Memory Write Client Description */
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#define TEGRA234_MEMORY_CLIENT_SESWR 0x81
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/* AXI AP and DFD-AUX0/1 read clients Both share the same interface on the on MSS */
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#define TEGRA234_MEMORY_CLIENT_AXIAPR 0x82
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/* AXI AP and DFD-AUX0/1 write clients Both sahre the same interface on MSS */
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#define TEGRA234_MEMORY_CLIENT_AXIAPW 0x83
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/* ETR read clients */
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#define TEGRA234_MEMORY_CLIENT_ETRR 0x84
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/* ETR write clients */
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#define TEGRA234_MEMORY_CLIENT_ETRW 0x85
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/* AXI Switch read client */
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#define TEGRA234_MEMORY_CLIENT_AXISR 0x8c
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/* AXI Switch write client */
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#define TEGRA234_MEMORY_CLIENT_AXISW 0x8d
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/* EQOS read client */
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#define TEGRA234_MEMORY_CLIENT_EQOSR 0x8e
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/* EQOS write client */
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#define TEGRA234_MEMORY_CLIENT_EQOSW 0x8f
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/* UFSHC read client */
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#define TEGRA234_MEMORY_CLIENT_UFSHCR 0x90
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/* UFSHC write client */
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#define TEGRA234_MEMORY_CLIENT_UFSHCW 0x91
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/* NVDISPLAY read client */
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#define TEGRA234_MEMORY_CLIENT_NVDISPLAYR 0x92
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/* AON read client */
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#define TEGRA234_MEMORY_CLIENT_AONR 0x97
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/* AON write client */
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#define TEGRA234_MEMORY_CLIENT_AONW 0x98
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/* AONDMA read client */
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#define TEGRA234_MEMORY_CLIENT_AONDMAR 0x99
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/* AONDMA write client */
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#define TEGRA234_MEMORY_CLIENT_AONDMAW 0x9a
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/* SCE read client */
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#define TEGRA234_MEMORY_CLIENT_SCER 0x9b
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/* SCE write client */
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#define TEGRA234_MEMORY_CLIENT_SCEW 0x9c
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/* SCEDMA read client */
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#define TEGRA234_MEMORY_CLIENT_SCEDMAR 0x9d
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/* SCEDMA write client */
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#define TEGRA234_MEMORY_CLIENT_SCEDMAW 0x9e
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/* NVDISPLAY read client instance 2 */
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#define TEGRA234_MEMORY_CLIENT_NVDISPLAYR1 0xa1
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#define TEGRA234_MEMORY_CLIENT_VICSRD1 0xa2
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/* MSS internal memqual MIU0 read clients */
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#define TEGRA234_MEMORY_CLIENT_MIU0R 0xa6
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/* MSS internal memqual MIU0 write clients */
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#define TEGRA234_MEMORY_CLIENT_MIU0W 0xa7
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/* MSS internal memqual MIU1 read clients */
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#define TEGRA234_MEMORY_CLIENT_MIU1R 0xa8
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/* MSS internal memqual MIU1 write clients */
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#define TEGRA234_MEMORY_CLIENT_MIU1W 0xa9
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/* MSS internal memqual MIU2 read clients */
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#define TEGRA234_MEMORY_CLIENT_MIU2R 0xae
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/* MSS internal memqual MIU2 write clients */
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#define TEGRA234_MEMORY_CLIENT_MIU2W 0xaf
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/* MSS internal memqual MIU3 read clients */
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#define TEGRA234_MEMORY_CLIENT_MIU3R 0xb0
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/* MSS internal memqual MIU3 write clients */
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#define TEGRA234_MEMORY_CLIENT_MIU3W 0xb1
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/* MSS internal memqual MIU4 read clients */
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#define TEGRA234_MEMORY_CLIENT_MIU4R 0xb2
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/* MSS internal memqual MIU4 write clients */
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#define TEGRA234_MEMORY_CLIENT_MIU4W 0xb3
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#define TEGRA234_MEMORY_CLIENT_DPMUR 0xb4
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#define TEGRA234_MEMORY_CLIENT_DPMUW 0xb5
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#define TEGRA234_MEMORY_CLIENT_NVL0R 0xb6
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#define TEGRA234_MEMORY_CLIENT_NVL0W 0xb7
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#define TEGRA234_MEMORY_CLIENT_NVL1R 0xb8
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#define TEGRA234_MEMORY_CLIENT_NVL1W 0xb9
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#define TEGRA234_MEMORY_CLIENT_NVL2R 0xba
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#define TEGRA234_MEMORY_CLIENT_NVL2W 0xbb
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/* VI FLACON read clients */
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#define TEGRA234_MEMORY_CLIENT_VIFALR 0xbc
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/* VIFAL write clients */
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#define TEGRA234_MEMORY_CLIENT_VIFALW 0xbd
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/* DLA0ARDA read clients */
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#define TEGRA234_MEMORY_CLIENT_DLA0RDA 0xbe
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/* DLA0 Falcon read clients */
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#define TEGRA234_MEMORY_CLIENT_DLA0FALRDB 0xbf
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/* DLA0 write clients */
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#define TEGRA234_MEMORY_CLIENT_DLA0WRA 0xc0
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/* DLA0 write clients */
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#define TEGRA234_MEMORY_CLIENT_DLA0FALWRB 0xc1
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/* DLA1ARDA read clients */
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#define TEGRA234_MEMORY_CLIENT_DLA1RDA 0xc2
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/* DLA1 Falcon read clients */
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#define TEGRA234_MEMORY_CLIENT_DLA1FALRDB 0xc3
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/* DLA1 write clients */
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#define TEGRA234_MEMORY_CLIENT_DLA1WRA 0xc4
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/* DLA1 write clients */
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#define TEGRA234_MEMORY_CLIENT_DLA1FALWRB 0xc5
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/* PVA0RDA read clients */
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#define TEGRA234_MEMORY_CLIENT_PVA0RDA 0xc6
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/* PVA0RDB read clients */
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#define TEGRA234_MEMORY_CLIENT_PVA0RDB 0xc7
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/* PVA0RDC read clients */
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#define TEGRA234_MEMORY_CLIENT_PVA0RDC 0xc8
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/* PVA0WRA write clients */
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#define TEGRA234_MEMORY_CLIENT_PVA0WRA 0xc9
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/* PVA0WRB write clients */
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#define TEGRA234_MEMORY_CLIENT_PVA0WRB 0xca
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/* PVA0WRC write clients */
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#define TEGRA234_MEMORY_CLIENT_PVA0WRC 0xcb
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/* RCE read client */
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#define TEGRA234_MEMORY_CLIENT_RCER 0xd2
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/* RCE write client */
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#define TEGRA234_MEMORY_CLIENT_RCEW 0xd3
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/* RCEDMA read client */
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#define TEGRA234_MEMORY_CLIENT_RCEDMAR 0xd4
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/* RCEDMA write client */
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#define TEGRA234_MEMORY_CLIENT_RCEDMAW 0xd5
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/* ISP read client 1 for Crossbar A */
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#define TEGRA234_MEMORY_CLIENT_ISPFALW 0xe4
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#define TEGRA234_MEMORY_CLIENT_NVL3R 0xe5
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#define TEGRA234_MEMORY_CLIENT_NVL3W 0xe6
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#define TEGRA234_MEMORY_CLIENT_NVL4R 0xe7
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#define TEGRA234_MEMORY_CLIENT_NVL4W 0xe8
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/* DLA0ARDA1 read clients */
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#define TEGRA234_MEMORY_CLIENT_DLA0RDA1 0xe9
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/* DLA1ARDA1 read clients */
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#define TEGRA234_MEMORY_CLIENT_DLA1RDA1 0xea
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/* PVA0RDA1 read clients */
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#define TEGRA234_MEMORY_CLIENT_PVA0RDA1 0xeb
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/* PVA0RDB1 read clients */
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#define TEGRA234_MEMORY_CLIENT_PVA0RDB1 0xec
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/* PCIE5r1 read clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE5R1 0xef
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#define TEGRA234_MEMORY_CLIENT_NVENCSRD1 0xf0
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/* ISP read client for Crossbar A */
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#define TEGRA234_MEMORY_CLIENT_ISPRA1 0xf2
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#define TEGRA234_MEMORY_CLIENT_NVL0RHP 0xf4
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#define TEGRA234_MEMORY_CLIENT_NVL1RHP 0xf5
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#define TEGRA234_MEMORY_CLIENT_NVL2RHP 0xf6
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#define TEGRA234_MEMORY_CLIENT_NVL3RHP 0xf7
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#define TEGRA234_MEMORY_CLIENT_NVL4RHP 0xf8
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/* MSS internal memqual MIU5 read clients */
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#define TEGRA234_MEMORY_CLIENT_MIU5R 0xfc
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/* MSS internal memqual MIU5 write clients */
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#define TEGRA234_MEMORY_CLIENT_MIU5W 0xfd
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/* MSS internal memqual MIU6 read clients */
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#define TEGRA234_MEMORY_CLIENT_MIU6R 0xfe
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/* MSS internal memqual MIU6 write clients */
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#define TEGRA234_MEMORY_CLIENT_MIU6W 0xff
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#endif /* DT_BINDINGS_MEMORY_TEGRA234_MC_OOT_H */
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