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2e68d82f52
Move files from private-soc to parent controller directory. Bug 5054840 Change-Id: I8ec5e5b34f2226bbbd051f4313033153a096e5c1 Signed-off-by: Prakhar Srivastava <prasrivastav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3312461 Reviewed-by: Bibek Basu <bbasu@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
128 lines
4.7 KiB
C
128 lines
4.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* SPDX-FileCopyrightText: Copyright (c) 2024-2025, NVIDIA CORPORATION. All rights reserved. */
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#ifndef TEGRA264_PCIE_XDMA_OSI_H
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#define TEGRA264_PCIE_XDMA_OSI_H
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#undef OSI_BIT
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#define OSI_BIT(b) (1U << (b))
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/** generates bit mask for 32 bit value */
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#undef OSI_GENMASK
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#define OSI_GENMASK(h, l) (((~0U) << (l)) & (~0U >> (31U - (h))))
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#define XDMA_MSI_CFG_MASK 0x100
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#define XDMA_MSI_CFG_MASK_STATUS_MSI BIT(8)
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#define XDMA_MSI_CFG_LOCAL_ADDRESS_LO 0x104
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#define XDMA_MSI_CFG_LOCAL_ADDRESS_HI 0x108
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#define XDMA_MSI_CFG_REMOTE_ADDRESS_LO 0x10c
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#define XDMA_MSI_CFG_REMOTE_ADDRESS_HI 0x110
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/* Channel specific registers */
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#define XDMA_CHANNEL_CTRL 0x2000
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#define XDMA_CHANNEL_CTRL_MSI_CHANNEL_NUMBER OSI_GENMASK(11, 9)
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#define XDMA_CHANNEL_CTRL_MSI_CHANNEL_SHIFT 9
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#define XDMA_CHANNEL_CTRL_DMA_CMD_SOURCE OSI_BIT(2)
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#define XDMA_CHANNEL_CTRL_DMA_OPERATION OSI_BIT(1)
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#define XDMA_CHANNEL_CTRL_EN OSI_BIT(0)
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#define XDMA_CHANNEL_DESCRIPTOR_LIST_POINTER_LOW 0x2020
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#define XDMA_CHANNEL_DESCRIPTOR_LIST_POINTER_HIGH 0x2040
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#define XDMA_CHANNEL_DESCRIPTOR_LIST_SIZE 0x2060
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#define XDMA_CHANNEL_DESCRIPTOR_LIST_SIZE_DESCRIPTOR_COUNT OSI_GENMASK(15, 0)
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#define XDMA_CHANNEL_SINGLE_TRANSFER_SOURCE_ADDRESS_LOW 0x2080
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#define XDMA_CHANNEL_SINGLE_TRANSFER_SOURCE_ADDRESS_HIGH 0x20a0
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#define XDMA_CHANNEL_SINGLE_TRANSFER_DESTINATION_ADDRESS_LOW 0x20c0
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#define XDMA_CHANNEL_SINGLE_TRANSFER_DESTINATION_ADDRESS_HIGH 0x2100
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#define XDMA_CHANNEL_SINGLE_TRANSFER_SIZE 0x2120
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#define XDMA_CHANNEL_TRANSFER_DOORBELL 0x2140
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#define XDMA_CHANNEL_TRANSFER_DOORBELL_DOORBELL BIT(0)
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#define XDMA_CHANNEL_TRANSFER_DOORBELL_NUM_DESC_ADDED GENMASK(15, 8)
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#define XDMA_CHANNEL_TRANSFER_DOORBELL_NUM_DESC_ADDED_SHIFT 8
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#define XDMA_CHANNEL_STATUS 0x2160
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#define XDMA_CHANNEL_STATUS_LAST_DESC_COMPLETED_ADDRESS_VALID BIT(9)
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#define XDMA_CHANNEL_STATUS_LAST_DESC_COMPLETED_ADDRESS_LO 0x2280
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#define XDMA_CHANNEL_STATUS_LAST_DESC_COMPLETED_ADDRESS_HI 0x22a0
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#define XDMA_CHANNEL_STATUS_LAST_DESC_COMPLETED_INDEX 0x22c0
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#define XDMA_CHANNEL_STATUS_LAST_DESC_COMPLETED_INDEX_VALUE GENMASK(15, 0)
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#define XDMA_CHANNEL_FUNC_ERROR_STATUS 0x23e0
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/* MSI channel registers */
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#define XDMA_MSI_CHANNEL_CFG_INTR 0x2420
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#define XDMA_MSI_CHANNEL_CFG_INTR_MASK OSI_BIT(0)
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#define XDMA_MSI_CHANNEL_CFG_INTR_DESTINATION OSI_BIT(1)
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#define XDMA_MSI_CHANNEL_CFG_INTR_ID 0x2440
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#define XDMA_MSI_CHANNEL_CFG_INTR_MOD 0x2460
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#define XDMA_MSI_CHANNEL_CFG_INTR_MOD_SCALE OSI_GENMASK(12, 10)
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#define XDMA_MSI_CHANNEL_CFG_INTR_ID_VALUE OSI_GENMASK(9, 0)
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#define XDMA_MSI_CHANNEL_PRIMARY_INTR_STATUS 0x2480
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#define XDMA_MSI_CHANNEL_PRIMARY_INTR_STATUS_INTR_START_PROCESSING OSI_BIT(0)
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#define XDMA_MSI_CHANNEL_PRIMARY_INTR_STATUS_INTR_END_PROCESSING OSI_BIT(1)
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#define XDMA_MSI_CHANNEL_PRIMARY_INTR_STATUS_FUNC_ERR_VALID OSI_GENMASK(15, 8)
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#define XDMA_MSI_CHANNEL_PRIMARY_INTR_STATUS_NEW_XFER_VALID OSI_GENMASK(23, 16)
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#define XDMA_CHANNEL_DEBUG_REGISTER_4 0x2580
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#define XDMA_CHANNEL_DEBUG_REGISTER_4_INTR_ENGINE_MSI_CHAN_ISR_INPROG_FSM GENMASK(3, 2)
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#define XDMA_CHANNEL_DEBUG_REGISTER_4_INTR_ENGINE_MSI_CHAN_MSI_DISP_FSM GENMASK(5, 4)
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#define XDMA_CHANNEL_DEBUG_REGISTER_4_INTR_ENGINE_MSI_CHAN_INTR_MOD_FSM BIT(6)
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#define XDMA_CHANNEL_DEBUG_REGISTER_4_INTR_ENGINE_MSI_CHAN_MSI_DISP_SHADOW_GEN_STATUS_MSI BIT(9)
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#define XDMA_CHANNEL_DEBUG_REGISTER_4_INTR_ENGINE_MSI_CHAN_MSI_DISP_SHADOW_FUNC_ERR_DETECTED BIT(8)
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struct xdma_attr {
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uint32_t wm:1;
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};
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struct xdma_hw_desc {
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volatile union {
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struct xdma_attr ctrl_e;
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uint32_t attr;
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} attr_reg;
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uint32_t sar_low;
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uint32_t sar_high;
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uint32_t dar_low;
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uint32_t dar_high;
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uint32_t size;
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uint32_t resv1;
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uint32_t resv2;
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};
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static inline unsigned int xdma_common_rd(void __iomem *p, unsigned int offset)
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{
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return readl(p + offset);
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}
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static inline void xdma_common_wr(void __iomem *p, unsigned int val, unsigned int offset)
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{
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writel(val, p + offset);
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}
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static inline void xdma_channel_wr(void __iomem *p, unsigned char c, unsigned int val, u32 offset)
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{
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writel(val, (0x4 * c) + p + offset);
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}
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static inline unsigned int xdma_channel_rd(void __iomem *p, unsigned char c, u32 offset)
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{
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return readl((0x4 * c) + p + offset);
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}
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irqreturn_t xdma_irq(int irq, void *cookie);
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irqreturn_t xdma_irq_handler(int irq, void *cookie);
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void *tegra264_pcie_xdma_initialize(struct tegra_pcie_dma_init_info *info, void *priv_dma);
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tegra_pcie_dma_status_t tegra264_pcie_xdma_set_msi(void *cookie, u64 msi_addr, u32 msi_data);
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tegra_pcie_dma_status_t tegra264_pcie_xdma_submit_xfer(void *cookie,
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struct tegra_pcie_dma_xfer_info *tx_info);
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bool tegra264_pcie_xdma_stop(void *cookie);
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void tegra264_pcie_xdma_deinit(void *cookie, void *priv_dma);
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#endif // TEGRA264_PCIE_XDMA_OSI_H
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