mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
synced 2025-12-23 01:31:30 +03:00
a23d954e3e
Add support to the bootstrap command over the admin channel, which will be called when a client registers. This command will perform steps that must be performed only after the client is ready. TODO: This bootstrap-2 command will be replaced by the existing bootstrap command which we call during DCE-FW bootstrapping once we split admin bootstrapping and RM bootstrapping in the DCE-KMD. Jira TDS-17135 Change-Id: I55330b9ce73e1acf20e2a80d392d7984c91ed65f Signed-off-by: Mahesh Kumar <mahkumar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3274949 Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: svcacv <svcacv@nvidia.com>
456 lines
13 KiB
C
456 lines
13 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2019-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef TEGRA_DCE_H
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#define TEGRA_DCE_H
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#include <dce-os-types.h>
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#include <dce-os-log.h>
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#include <dce-ipc.h>
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#include <dce-hsp.h>
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#include <dce-os-lock.h>
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#include <dce-os-cond.h>
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#include <dce-regs.h>
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#include <dce-wait-cond.h>
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#include <dce-fsm.h>
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#include <dce-pm.h>
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#include <dce-mailbox.h>
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#include <dce-client-ipc-internal.h>
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#include <dce-os-work.h>
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#define DCE_WARN_ON_NOT_NULL(x) \
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do { \
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if (x != NULL) { \
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dce_os_warn(d, "Unexpected non-NULL value for " #x "\n"); \
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} \
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} while (0)
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#define DCE_WARN_ON_NULL(x) \
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do { \
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if (x == NULL) { \
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dce_os_warn(d, "Unexpected NULL value for " #x "\n"); \
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} \
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} while (0)
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#define DCE_MAX_CPU_IRQS 4
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/**
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* DCE Boot Status : DCE Driver Init States
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*
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* @DCE_EARLY_INIT_* : Driver Init Before Bootstrap
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* @DCE_AST_CONFIG_* : Used When DCE-CPU Driver Loads the Firmware
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*/
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#define DCE_EARLY_INIT_START DCE_BIT(31)
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#define DCE_EARLY_INIT_FAILED DCE_BIT(30)
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#define DCE_EARLY_INIT_DONE DCE_BIT(29)
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#define DCE_AST_CONFIG_START DCE_BIT(28)
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#define DCE_AST_CONFIG_FAILED DCE_BIT(27)
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#define DCE_AST_CONFIG_DONE DCE_BIT(26)
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/**
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* DCE Boot Status: FW Boot States
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*/
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#define DCE_FW_EARLY_BOOT_START DCE_BIT(16)
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#define DCE_FW_EARLY_BOOT_FAILED DCE_BIT(15)
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#define DCE_FW_EARLY_BOOT_DONE DCE_BIT(14)
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#define DCE_FW_BOOTSTRAP_START DCE_BIT(13)
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#define DCE_FW_BOOTSTRAP_FAILED DCE_BIT(12)
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#define DCE_FW_BOOTSTRAP_DONE DCE_BIT(11)
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#define DCE_FW_ADMIN_SEQ_START DCE_BIT(10)
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#define DCE_FW_ADMIN_SEQ_FAILED DCE_BIT(9)
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#define DCE_FW_ADMIN_SEQ_DONE DCE_BIT(8)
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#define DCE_FW_SUSPENDED DCE_BIT(2)
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#define DCE_FW_BOOT_DONE DCE_BIT(1)
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#define DCE_STATUS_FAILED DCE_BIT(0)
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#define DCE_STATUS_UNKNOWN ((u32)(0))
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/**
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* DCE Admin channel client buffer IDs.
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* These are also indices to buffers in
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* tegra_dce's admin_cl_msg_buffer[]
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*/
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#define DCE_ADMIN_CH_CL_ADMIN_BUFF 0U
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#define DCE_ADMIN_CH_CL_PM_BUFF 1U
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#define DCE_ADMIN_CH_CL_DBG_BUFF 2U
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#define DCE_ADMIN_CH_CL_DBG_PERF_BUFF 3U
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#define DCE_ADMIN_CH_CL_MAX 4U
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/**
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* DCE Admin channel client buffer counts.
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* These indicate buffers reserved for
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* respective DCE admin channel client.
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*/
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#define DCE_ADMIN_CH_CL_ADMIN_BUFF_COUNT 1U
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#define DCE_ADMIN_CH_CL_PM_BUFF_COUNT 1U
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#define DCE_ADMIN_CH_CL_DBG_BUFF_COUNT 1U
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#define DCE_ADMIN_CH_CL_DBG_PERF_BUFF_COUNT 1U
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/**
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* DCE Wait condition IDs.
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*/
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#define DCE_WAIT_BOOT_COMPLETE 0
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#define DCE_WAIT_BOOT_CMD 1
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#define DCE_WAIT_ADMIN_IPC 2
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#define DCE_WAIT_SC7_ENTER 3
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#define DCE_WAIT_LOG 4
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#define DCE_MAX_WAIT 5
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struct tegra_dce;
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/**
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* struct dce_admin_ch_cl_buff - DCE Admin channel client buffer.
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*/
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struct dce_admin_ch_cl_buff {
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/**
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* @msg : DCE IPC message buffer.
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*/
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struct dce_ipc_message msg;
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/**
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* @in_use : Indicates if this buffer is in use.
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*/
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dce_os_atomic_t in_use;
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};
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/**
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* struct dce_platform_data - Data Structure to hold platform specific DCE
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* cluster data.
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*/
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struct dce_platform_data {
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/**
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* @fw_dce_addr : Stores the firmware address that DCE sees before being
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* converted by AST.
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*/
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u32 fw_dce_addr;
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/**
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* fw_image_size : Stores the max size of DCE fw.
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*/
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u32 fw_img_size;
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/**
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* @fw_info_valid : Tells if the above address and size info are valid.
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* CPU driver will use this info just for debug purpose.
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*/
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bool fw_info_valid;
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/**
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* @no_of_asts : Stores max no. of ASTs in the DCE Cluster
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*/
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u8 no_of_asts;
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/**
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* phys_stream_id : Physical stream ID to be programmed for debug
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* purpose only.
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*/
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u32 phys_stream_id;
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/**
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* stream_id : Stream ID to program the ASTs in debug mode
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* only.
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*/
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u8 stream_id;
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/**
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* hsp_id - HSP instance id used for dce communication
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*/
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u32 hsp_id;
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/**
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* fw_vmindex : VMIndex to program the AST region to read FW in debug
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* mode only.
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*/
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u8 fw_vmindex;
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/**
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* fw_carveout_id : Carveout ID to program the AST region to read FW in
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* debug mode only.
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*/
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u8 fw_carveout_id;
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/**
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* @fw_name : Stores dce fw name
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*/
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const char *fw_name;
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/**
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* @use_physical_id : Use physical streamid
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*/
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bool use_physical_id;
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};
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/**
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* struct dce_firmware - Contains dce firmware info
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*
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* @data : u8 pointer to hold the fw data
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* @size : size of the fw
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* @dma_handle : stores the dma_handle for firmware
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*/
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struct dce_firmware {
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u8 *data;
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size_t size;
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u64 dma_handle;
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};
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/**
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* struct tegra_dce - Primary OS independent tegra dce structure to hold dce
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* cluster's and it's element's runtime info.
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*/
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struct tegra_dce {
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/**
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* @irq - Array of irqs to be handled by cpu from dce cluster.
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*/
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u32 irq[DCE_MAX_CPU_IRQS];
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/**
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* @fsm_info - Data Structure to manage dce FSM states.
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*/
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struct dce_fsm_info fsm_info;
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/**
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* dce_bootstrap_work : dce work to be executed to start FSM flow
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*/
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dce_os_work_handle_t dce_bootstrap_work;
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/**
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* dce_resume_work : dce work to executed dce resume flow
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*/
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dce_os_work_handle_t dce_resume_work;
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/**
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* dce_sc7_state : structure to save/restore state during sc7 enter/exit
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*/
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struct dce_sc7_state sc7_state;
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/**
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* dce_wait_info - Data structure to manage wait for different event types
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*/
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struct dce_wait_cond ipc_waits[DCE_MAX_WAIT];
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/**
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* dce_bootstrap_done - Data structure to manage wait for boot done
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*/
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struct dce_os_cond dce_bootstrap_done;
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/**
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* @d_mb - Stores the current status of dce mailbox interfaces.
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*/
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struct dce_mailbox_interface d_mb[DCE_MAILBOX_MAX_INTERFACES];
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/**
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* @d_ipc - Stores the ipc related data between CPU and DCE.
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*/
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struct dce_ipc d_ipc;
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/**
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* @d_clients - Stores all dce clients data.
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*/
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struct tegra_dce_client_ipc *d_clients[DCE_CLIENT_IPC_TYPE_MAX];
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/**
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* @d_async_ipc_info - stores data to handle async events
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*/
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struct tegra_dce_async_ipc_info d_async_ipc;
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/**
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* @hsp_id - HSP instance id used for dce communication
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*/
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u32 hsp_id;
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/**
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* @hsp - Struct to store function pointers for HSP access.
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*/
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struct dce_hsp_fn hsp;
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/**
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* @boot_status - u32 variable to store dce's boot status.
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*/
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u32 boot_status;
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/**
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* @boot_complete - Boolean variable to store dce's boot status.
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*/
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bool boot_complete;
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/**
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* @ast_config_complete - Boolean variable to store dce's ast
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* configuration status.
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*/
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bool ast_config_complete;
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/**
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* @reset_complete - Boolean variable to store dce's reset status.
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*/
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bool reset_complete;
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/**
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* @load_complete - Boolean variable to store dce's fw load status.
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*/
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bool load_complete;
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/**
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* @log_level - Stores the log level for dce cpu prints.
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*/
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u32 log_level;
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/**
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* @fw_data - Stores info regardign firmware to be used runtime.
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*/
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struct dce_firmware *fw_data;
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/**
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* @dce_admin_ch_cl_buff - Stores admin channel client buffers.
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*/
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struct dce_admin_ch_cl_buff **admin_ch_cl_buff[DCE_ADMIN_CH_CL_MAX];
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};
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/**
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* dce_set_boot_complete - updates the current dce boot complete status.
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*
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* @d : Pointer to tegra_dce struct.
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* @val : true or false.
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*
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* Return : void
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*/
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static inline void dce_set_boot_complete(struct tegra_dce *d, bool val)
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{
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d->boot_complete = val;
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if (!val)
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d->boot_status &= (~DCE_FW_BOOT_DONE);
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}
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/**
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* dce_is_bootcmds_done - Checks if dce bootstrap bootcmds done.
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*
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* Chekc if all the mailbox boot commands are completed
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*
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* @d - Pointer to tegra_dce struct.
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*
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* Return : True if bootcmds are completed
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*/
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static inline bool dce_is_bootcmds_done(struct tegra_dce *d)
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{
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return (d->boot_status & DCE_FW_BOOTSTRAP_DONE) ? true : false;
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}
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/**
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* dce_is_bootstrap_done - check if dce bootstrap is done.
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*
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* @d : Pointer to tegra_dce struct.
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*
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* Return : true if bootstrap done else false
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*/
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static inline bool dce_is_bootstrap_done(struct tegra_dce *d)
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{
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return (d->boot_status & DCE_FW_BOOT_DONE) ? true : false;
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}
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/**
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* dce_set_ast_config_status - updates the current status of ast configuration.
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*
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* @d : Pointer to tegra_dce struct.
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* @val : true or false.
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*
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* Return : void
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*/
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static inline void dce_set_ast_config_status(struct tegra_dce *d, bool val)
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{
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d->ast_config_complete = val;
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}
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/**
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* dce_set_dce_reset_status - updates the current status of dce reset.
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*
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* @d : Pointer to tegra_dce struct.
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* @val : true or false.
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*
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* Return : void
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*/
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static inline void dce_set_dce_reset_status(struct tegra_dce *d, bool val)
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{
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d->reset_complete = val;
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}
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/**
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* dce_set_load_fw_status - updates the current status of fw loading.
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*
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* @d : Pointer to tegra_dce struct.
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* @val : true or false stating fw load is complete or incomplete respectiveely.
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*
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* Return : void
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*/
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static inline void dce_set_load_fw_status(struct tegra_dce *d, bool val)
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{
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d->load_complete = val;
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}
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/**
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* Common Utility Functions. Description can be found with
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* function definitions.
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*/
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void dce_driver_start(struct tegra_dce *d);
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void dce_driver_stop(struct tegra_dce *d);
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int dce_driver_init(struct tegra_dce *d);
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void dce_driver_deinit(struct tegra_dce *d);
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int dce_start_boot_flow(struct tegra_dce *d);
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int dce_start_bootstrap_flow(struct tegra_dce *d);
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int dce_boot_interface_init(struct tegra_dce *d);
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void dce_boot_interface_deinit(struct tegra_dce *d);
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int dce_handle_boot_cmd_requested_event(struct tegra_dce *d, void *params);
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int dce_handle_boot_cmd_received_event(struct tegra_dce *d, void *params);
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int dce_handle_boot_complete_requested_event(struct tegra_dce *d, void *params);
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int dce_handle_boot_complete_received_event(struct tegra_dce *d, void *params);
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int dce_admin_init(struct tegra_dce *d);
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void dce_admin_deinit(struct tegra_dce *d);
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int dce_start_admin_seq(struct tegra_dce *d);
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int dce_admin_send_msg(struct tegra_dce *d,
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struct dce_ipc_message *msg);
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void dce_admin_ivc_channel_reset(struct tegra_dce *d);
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int dce_admin_get_ipc_channel_info(struct tegra_dce *d,
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struct dce_ipc_queue_info *q_info);
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int dce_admin_send_cmd_echo(struct tegra_dce *d,
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struct dce_ipc_message *msg);
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int dce_admin_send_cmd_rm_bootstrap(struct tegra_dce *d,
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struct dce_ipc_message *msg);
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int dce_admin_send_cmd_ext_test(struct tegra_dce *d,
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struct dce_ipc_message *msg);
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int dce_admin_send_prepare_sc7(struct tegra_dce *d,
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struct dce_ipc_message *msg);
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int dce_admin_send_enter_sc7(struct tegra_dce *d,
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struct dce_ipc_message *msg);
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int dce_admin_handle_ipc_requested_event(struct tegra_dce *d, void *params);
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int dce_admin_handle_ipc_received_event(struct tegra_dce *d, void *params);
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int dce_admin_send_cmd_get_perf_stat(struct tegra_dce *d,
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struct dce_ipc_message *msg);
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int dce_admin_send_cmd_set_perf_stat(struct tegra_dce *d,
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struct dce_ipc_message *msg,
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bool start_perf);
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int dce_admin_send_cmd_stop_perf_stat(struct tegra_dce *d,
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struct dce_ipc_message *msg);
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int dce_admin_send_cmd_get_perf_events(struct tegra_dce *d,
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struct dce_ipc_message *msg);
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int dce_admin_send_cmd_clear_perf_events(struct tegra_dce *d,
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struct dce_ipc_message *msg);
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int dce_admin_ipc_wait(struct tegra_dce *d);
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void dce_admin_ipc_handle_signal(struct tegra_dce *d, u32 ch_type);
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bool dce_fw_boot_complete(struct tegra_dce *d);
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void dce_request_fw_boot_complete(struct tegra_dce *d);
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int dce_admin_channel_client_buffers_init(struct tegra_dce *d, u32 cl_id);
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void dce_admin_channel_client_buffers_deinit(struct tegra_dce *d, u32 cl_id);
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struct dce_ipc_message *dce_admin_channel_client_buffer_get(
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struct tegra_dce *d, u32 cl_id, u32 flags);
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void dce_admin_channel_client_buffer_put(
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struct tegra_dce *d, struct dce_ipc_message *pmsg);
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int dce_waiters_init(struct tegra_dce *d);
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void dce_waiters_deinit(struct tegra_dce *d);
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/**
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* Functions to be used in debug mode only.
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*
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* TODO : Have sanity checks for these not to be
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* used in non-debug mode.
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*/
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void dce_config_ast(struct tegra_dce *d);
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int dce_reset_dce(struct tegra_dce *d);
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#ifdef CONFIG_DEBUG_FS
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void dce_init_debug(struct tegra_dce *d);
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void dce_remove_debug(struct tegra_dce *d);
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#endif
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#endif
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