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git://nv-tegra.nvidia.com/linux-nv-oot.git
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4b5bdb9393
With Linux v6.13, the Tegra264 NVADSP driver fails to build and the
following errors are observed:
In file included from drivers/platform/tegra/nvadsp/dev-t264.c:4:
include/linux/reset.h:30:49: error: implicit declaration of function
‘BIT’ [-Werror=implicit-function-declaration]
30 | #define RESET_CONTROL_FLAGS_BIT_ACQUIRED BIT(2)
| ^~~
In file included from drivers/platform/tegra/nvadsp/dev-t264-aon.c:4:
/include/linux/reset.h:30:49: error: implicit declaration of function
‘BIT’ [-Werror=implicit-function-declaration]
30 | #define RESET_CONTROL_FLAGS_BIT_ACQUIRED BIT(2)
| ^~~
Fix this by adding the missing 'bits.h' header.
Bug 4991705
Change-Id: I08a6cb59339f8e5221fdc3f39b2a7323cae0cd1f
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3261688
Reviewed-by: svcacv <svcacv@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Viswanath L <viswanathl@nvidia.com>
254 lines
6.1 KiB
C
254 lines
6.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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// SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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#include <linux/bits.h>
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#include <linux/reset.h>
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#include <soc/tegra/virt/hv-ivc.h>
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#include "dev.h"
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#include "hwmailbox.h"
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#include "os.h"
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#define AMISC_ADSP_CPU_CONFIG (0x0)
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#define AMISC_ADSP_STATVECTORSEL (1 << 4)
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#define AMISC_ADSP_RUNSTALL (1 << 0)
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#define AMISC_ADSP_CPU_RESETVEC (0x4)
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#define AMISC_ADSP_CPU_IDLE_STATUS (0x2c)
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static int nvadsp_os_t264_init(struct platform_device *pdev)
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{
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struct nvadsp_drv_data *drv_data = platform_get_drvdata(pdev);
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int ret = 0, val = 0;
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if (drv_data->chip_data->adsp_os_config_hwmbox != 0) {
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if (is_tegra_hypervisor_mode()) {
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/* Set ADSP to know its virtualized configuration */
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val = ADSP_CONFIG_VIRT_EN << ADSP_CONFIG_VIRT_SHIFT;
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/* Write to HWMBOX */
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hwmbox_writel(drv_data, val,
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drv_data->chip_data->adsp_os_config_hwmbox);
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}
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}
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return ret;
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}
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#ifdef CONFIG_PM
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static int nvadsp_t264_clocks_disable(struct platform_device *pdev)
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{
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/* TBD */
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return 0;
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}
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static int nvadsp_t264_clocks_enable(struct platform_device *pdev)
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{
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/* TBD */
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return 0;
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}
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static int __nvadsp_t264_runtime_resume(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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int ret;
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dev_dbg(dev, "at %s:%d\n", __func__, __LINE__);
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ret = nvadsp_t264_clocks_enable(pdev);
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if (ret) {
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dev_dbg(dev, "failed in nvadsp_t264_clocks_enable\n");
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return ret;
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}
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return ret;
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}
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static int __nvadsp_t264_runtime_suspend(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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dev_dbg(dev, "at %s:%d\n", __func__, __LINE__);
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return nvadsp_t264_clocks_disable(pdev);
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}
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static int __nvadsp_t264_runtime_idle(struct device *dev)
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{
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dev_dbg(dev, "at %s:%d\n", __func__, __LINE__);
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return 0;
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}
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static int nvadsp_pm_t264_init(struct platform_device *pdev)
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{
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struct nvadsp_drv_data *d = platform_get_drvdata(pdev);
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struct device *dev = &pdev->dev;
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dev_dbg(dev, "at %s:%d\n", __func__, __LINE__);
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d->runtime_suspend = __nvadsp_t264_runtime_suspend;
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d->runtime_resume = __nvadsp_t264_runtime_resume;
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d->runtime_idle = __nvadsp_t264_runtime_idle;
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return 0;
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}
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#endif /* CONFIG_PM */
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static void __dump_core_state_t264(struct nvadsp_drv_data *d)
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{
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/* TBD */
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}
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static int __set_boot_vec_t264(struct nvadsp_drv_data *d)
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{
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/* TBD */
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return 0;
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}
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static int __set_boot_freqs_t264(struct nvadsp_drv_data *d)
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{
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/* TBD */
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return 0;
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}
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static int __assert_t264_adsp(struct nvadsp_drv_data *d)
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{
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struct platform_device *pdev = d->pdev;
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struct device *dev = &pdev->dev;
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void __iomem *cpu_config_base;
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u32 cpu_config;
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int ret = 0;
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/* Assert RUNSTALL */
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cpu_config_base = d->base_regs[AMISC];
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cpu_config = readl(cpu_config_base + AMISC_ADSP_CPU_CONFIG);
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cpu_config |= AMISC_ADSP_RUNSTALL;
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writel(cpu_config, cpu_config_base + AMISC_ADSP_CPU_CONFIG);
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/* CAR assert */
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ret = reset_control_assert(d->adspall_rst);
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if (ret)
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dev_err(dev, "failed to assert adsp: %d\n", ret);
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return ret;
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}
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static int __deassert_t264_adsp(struct nvadsp_drv_data *d)
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{
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struct platform_device *pdev = d->pdev;
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struct device *dev = &pdev->dev;
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void __iomem *cpu_config_base;
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u32 cpu_config;
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int ret = 0;
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/* CAR deassert */
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ret = reset_control_deassert(d->adspall_rst);
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if (ret) {
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dev_err(dev, "failed to deassert adsp: %d\n", ret);
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goto end;
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}
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/* Deassert RUNSTALL */
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cpu_config_base = d->base_regs[AMISC];
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cpu_config = readl(cpu_config_base + AMISC_ADSP_CPU_CONFIG);
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cpu_config &= (~AMISC_ADSP_RUNSTALL);
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writel(cpu_config, cpu_config_base + AMISC_ADSP_CPU_CONFIG);
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end:
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return ret;
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}
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static bool __check_wfi_status_t264(struct nvadsp_drv_data *d)
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{
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void __iomem *cpu_config_base;
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bool wfi_status = false;
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u8 cnt = 5;
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cpu_config_base = d->base_regs[AMISC];
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while (cnt > 0) {
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wfi_status = readl(cpu_config_base + AMISC_ADSP_CPU_IDLE_STATUS);
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if (wfi_status)
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return wfi_status;
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cnt--;
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}
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return wfi_status;
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}
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static int nvadsp_dev_t264_init(struct platform_device *pdev)
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{
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struct nvadsp_drv_data *d = platform_get_drvdata(pdev);
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struct device *dev = &pdev->dev;
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int ret = 0;
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d->assert_adsp = __assert_t264_adsp;
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d->deassert_adsp = __deassert_t264_adsp;
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d->set_boot_vec = __set_boot_vec_t264;
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d->set_boot_freqs = __set_boot_freqs_t264;
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d->check_wfi_status = __check_wfi_status_t264;
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d->dump_core_state = __dump_core_state_t264;
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d->adspall_rst = devm_reset_control_get(dev, "adsp");
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if (IS_ERR(d->adspall_rst)) {
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dev_err(dev, "cannot get adsp reset\n");
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ret = PTR_ERR(d->adspall_rst);
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}
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return ret;
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}
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struct nvadsp_chipdata tegra264_adsp0_chipdata = {
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.hwmb = {
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.reg_idx = AHSP,
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.hwmbox0_reg = 0x00000,
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.hwmbox1_reg = 0X08000,
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.hwmbox2_reg = 0X10000,
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.hwmbox3_reg = 0X18000,
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.hwmbox4_reg = 0X20000,
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.hwmbox5_reg = 0X28000,
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.hwmbox6_reg = 0X30000,
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.hwmbox7_reg = 0X38000,
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.empty_int_ie = 0x8,
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},
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.adsp_shared_mem_hwmbox = 0x08048, /* HWMBOX1 TYPE1_DATA0 */
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.adsp_boot_config_hwmbox = 0x0804C, /* HWMBOX1 TYPE1_DATA1 */
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.adsp_cpu_freq_hwmbox = 0x08050, /* HWMBOX1 TYPE1_DATA2 */
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.adsp_os_config_hwmbox = 0x08054, /* HWMBOX1 TYPE1_DATA3 */
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.dev_init = nvadsp_dev_t264_init,
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.os_init = nvadsp_os_t264_init,
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#ifdef CONFIG_PM
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.pm_init = nvadsp_pm_t264_init,
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#endif
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.adsp_elf = "adsp0_t264.elf",
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.num_irqs = NVADSP_VIRQ_MAX,
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};
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struct nvadsp_chipdata tegra264_adsp1_chipdata = {
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.hwmb = {
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.reg_idx = AHSP,
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.hwmbox0_reg = 0x00000,
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.hwmbox1_reg = 0X08000,
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.hwmbox2_reg = 0X10000,
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.hwmbox3_reg = 0X18000,
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.hwmbox4_reg = 0X20000,
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.hwmbox5_reg = 0X28000,
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.hwmbox6_reg = 0X30000,
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.hwmbox7_reg = 0X38000,
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.empty_int_ie = 0x8,
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},
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.adsp_shared_mem_hwmbox = 0x08048, /* HWMBOX1 TYPE1_DATA0 */
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.adsp_boot_config_hwmbox = 0x0804C, /* HWMBOX1 TYPE1_DATA1 */
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.adsp_cpu_freq_hwmbox = 0x08050, /* HWMBOX1 TYPE1_DATA2 */
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.adsp_os_config_hwmbox = 0x08054, /* HWMBOX1 TYPE1_DATA3 */
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.dev_init = nvadsp_dev_t264_init,
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.os_init = nvadsp_os_t264_init,
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#ifdef CONFIG_PM
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.pm_init = nvadsp_pm_t264_init,
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#endif
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.adsp_elf = "adsp1_t264.elf",
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.num_irqs = NVADSP_VIRQ_MAX,
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.amc_not_avlbl = true,
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};
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