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adc35280cb
Enable WDR(wide dynamic range) mode for IMX390. The following modification and addition are done: 1 Add WDR mode table 2 Restructure IMX390 driver for WDR gain and framerate 3 Use common driver to configure serializer(max9295) and deserializer(max9296) Bug 4505240 Change-Id: I52fc3f03a66fe4e2446d7b41f409ed4154c42f02 Signed-off-by: Ankur Pawar <ankurp@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3105249 Reviewed-by: Narendra Kondapalli <nkondapalli@nvidia.com> Reviewed-by: Shubham Chandra <shubhamc@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Praveen AC <pac@nvidia.com>
153 lines
3.8 KiB
C
153 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
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#ifndef __MAX929X_H__
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#define __MAX929X_H__
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/* TI FPD Link III 954 deser I2C address */
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#define TI954_ADDR (0x30)
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/* TI FPD Link III 953 ser I2C address */
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#define TI953_ADDR (0x18)
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/* TI 953 alias address */
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#define TI953_CAM1_ADDR (0x29)
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#define TI953_CAM2_ADDR (0X2A)
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#define MAX9295_DEV_ADDR 0x00
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#define SENSOR_ADDR (0x1a)
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/* CAM alias address */
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#define CAM1_SENSOR_ADDR (0x1b)
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#define CAM2_SENSOR_ADDR (0x1c)
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#define TI954_RESET_ADDR (0x01)
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#define TI954_RESET_VAL (0x02)
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#define AFDRV_I2C_ADDR (0x3E)
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/*AF ctrl*/
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#define AFDRV1_I2C_ADDR (0x21)
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#define AFDRV2_I2C_ADDR (0x20)
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#define EEPROM_I2C_ADDR (0x50)
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/*eeprom ctrl*/
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#define EEPROM1_I2C_ADDR (0x51)
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#define EEPROM2_I2C_ADDR (0x52)
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struct max929x_reg {
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u8 slave_addr;
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u16 reg;
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u8 val;
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};
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/* Serializer slave addresses */
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#define SER_SLAVE1 0x40
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#define SER_SLAVE2 0x62
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/* Deserializer slave addresses */
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#define DESER_SLAVE 0x48
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/*
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* MAX9296 i2c addr 0x90(8bits) 0x48(7bits)
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* (MAX9296 link A) MAX9295 i2c addr 0xc4(8bits) 0x62(7bits)
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*/
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static struct max929x_reg max929x_Double_Dser_Ser_init[] = {
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/* set MFP0 low to reset sensor */
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{0x62, 0x02be, 0x80},
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/* Set SER to 1x4 mode (phy_config = 0) */
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{0x62, 0x0330, 0x00},
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{0x62, 0x0332, 0xe4},
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/* Additional lane map */
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{0x62, 0x0333, 0xe4},
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/* Set 4 lanes for serializer (ctrl1_num_lanes = 3) */
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{0x62, 0x0331, 0x31},
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/* Start video from both port A and port B. */
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{0x62, 0x0311, 0x20},
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/*
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* Enable info lines. Additional start bits for Port A and B.
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* Use data from port B for all pipelines
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*/
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{0x62, 0x0308, 0x62},
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/* Route 16bit DCG (DT = 0x30) to VIDEO_X (Bit 6 enable) */
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{0x62, 0x0314, 0x22},
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/* Route 12bit RAW (DT = 0x2C) to VIDEO_Y (Bit 6 enable) */
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{0x62, 0x0316, 0x6c},
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/* Route EMBEDDED8 to VIDEO_Z (Bit 6 enable) */
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{0x62, 0x0318, 0x22},
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/* Unused VIDEO_U */
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{0x62, 0x031A, 0x22},
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/*
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* Make sure all pipelines start transmission
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* (VID_TX_EN_X/Y/Z/U = 1)
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*/
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{0x62, 0x0002, 0x22},
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/* Set MIPI Phy Mode: 2x(1x4) mode */
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{0x48, 0x0330, 0x04},
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/* lane maps - all 4 ports mapped straight */
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{0x48, 0x0333, 0x4E},
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/* Additional lane map */
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{0x48, 0x0334, 0xE4},
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/*
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* lane count - 0 lanes striping on controller 0
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* (Port A slave in 2x1x4 mode).
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*/
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{0x48, 0x040A, 0x00},
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/*
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* lane count - 4 lanes striping on controller 1
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* (Port A master in 2x1x4 mode).
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*/
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{0x48, 0x044A, 0xd0},
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/*
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* lane count - 4 lanes striping on controller 2
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* (Port B master in 2x1x4 mode).
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*/
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{0x48, 0x048A, 0xd0},
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/*
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* lane count - 0 lanes striping on controller 3
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* (Port B slave in 2x1x4 mode).
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*/
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{0x48, 0x04CA, 0x00},
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/*
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* MIPI clock rate - 1.5Gbps from controller 0 clock
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* (Port A slave in 2x1x4 mode).
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*/
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{0x48, 0x031D, 0x2f},
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/*
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* MIPI clock rate - 1.5Gbps from controller 1 clock
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* (Port A master in 2x1x4 mode).
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*/
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{0x48, 0x0320, 0x2f},
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/*
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* MIPI clock rate - 1.5Gbps from controller 2 clock
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* (Port B master in 2x1x4 mode).
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*/
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{0x48, 0x0323, 0x2f},
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/*
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* MIPI clock rate - 1.5Gbps from controller 2 clock
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* (Port B slave in 2x1x4 mode).
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*/
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{0x48, 0x0326, 0x2f},
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/* Route data from stream 0 to pipe X */
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{0x48, 0x0050, 0x00},
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/* Route data from stream 0 to pipe Y */
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{0x48, 0x0051, 0x01},
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/* Route data from stream 0 to pipe Z */
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{0x48, 0x0052, 0x02},
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/* Route data from stream 0 to pipe U */
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{0x48, 0x0053, 0x03},
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/* Enable all PHYS. */
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{0x48, 0x0332, 0xF0},
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/* Enable sensor power down pin. Put imager in,Active mode */
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{0x62, 0x02be, 0x90},
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/* Output RCLK to sensor. */
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{0x62, 0x03F1, 0x89},
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/* MFP8 for FSIN */
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{0x62, 0x02D8, 0x10},
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{0x62, 0x02D6, 0x04},
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/* need disable pixel clk out inb order to use MFP1 */
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{0x48, 0x0005, 0x00},
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/* GPIO TX compensation */
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{0x48, 0x02B3, 0x83},
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{0x48, 0x02B4, 0x10},
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};
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#endif
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