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97835cded8
Bug 4165184 Change-Id: Id5d570cc4e5c3364d696271b1333e47e02e17b9e Signed-off-by: Chris Dragan <kdragan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2976924 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
137 lines
3.5 KiB
C
137 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* SPDX-FileCopyrightText: Copyright (c) 2017-2023, NVIDIA CORPORATION. All rights reserved. */
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#include "mods_internal.h"
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#include <linux/err.h>
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#ifdef MODS_ENABLE_BPMP_MRQ_API
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static int tegra_pcie_bpmp_set_ctrl_state(struct mods_smmu_dev *pcie_dev,
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bool enable)
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{
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struct mrq_uphy_response resp;
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struct tegra_bpmp_message msg;
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struct mrq_uphy_request req;
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memset(&req, 0, sizeof(req));
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memset(&resp, 0, sizeof(resp));
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req.cmd = CMD_UPHY_PCIE_CONTROLLER_STATE;
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req.controller_state.pcie_controller = pcie_dev->cid;
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req.controller_state.enable = enable;
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memset(&msg, 0, sizeof(msg));
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msg.mrq = MRQ_UPHY;
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msg.tx.data = &req;
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msg.tx.size = sizeof(req);
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msg.rx.data = &resp;
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msg.rx.size = sizeof(resp);
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return tegra_bpmp_transfer(pcie_dev->bpmp, &msg);
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}
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static int uphy_bpmp_pcie_controller_state_set(int controller, int enable)
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{
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#define MAX_DEV_NAME_LEN 32
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char dev_name[MAX_DEV_NAME_LEN];
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struct mods_smmu_dev *smmu_pdev = NULL;
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int smmudev_idx, n;
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memset(dev_name, 0, MAX_DEV_NAME_LEN);
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n = snprintf(dev_name, MAX_DEV_NAME_LEN, "mods_pcie%d", controller);
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if (n < 0 || n >= MAX_DEV_NAME_LEN)
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return -EINVAL;
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smmudev_idx = get_mods_smmu_device_index(dev_name);
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if (smmudev_idx >= 0)
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smmu_pdev = get_mods_smmu_device(smmudev_idx);
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if (!smmu_pdev || smmudev_idx < 0) {
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mods_error_printk("smmu device %s is not found\n", dev_name);
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return -ENODEV;
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}
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smmu_pdev->cid = controller;
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return tegra_pcie_bpmp_set_ctrl_state(smmu_pdev, enable);
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}
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#else
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static int uphy_bpmp_pcie_controller_state_set(int controller, int enable)
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{
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mods_error_printk("bpmp mrq api is not supported\n");
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return -ENODEV;
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}
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#endif
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int esc_mods_bpmp_set_pcie_state(
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struct mods_client *client,
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struct MODS_SET_PCIE_STATE *p
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)
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{
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return uphy_bpmp_pcie_controller_state_set(p->controller, p->enable);
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}
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#ifdef MODS_ENABLE_BPMP_MRQ_API
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static int tegra_pcie_bpmp_set_pll_state(struct mods_smmu_dev *pcie_dev,
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bool enable)
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{
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struct mrq_uphy_response resp;
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struct tegra_bpmp_message msg;
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struct mrq_uphy_request req;
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memset(&req, 0, sizeof(req));
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memset(&resp, 0, sizeof(resp));
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if (enable) {
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req.cmd = CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT;
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req.ep_ctrlr_pll_init.ep_controller = pcie_dev->cid;
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} else {
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req.cmd = CMD_UPHY_PCIE_EP_CONTROLLER_PLL_OFF;
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req.ep_ctrlr_pll_off.ep_controller = pcie_dev->cid;
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}
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memset(&msg, 0, sizeof(msg));
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msg.mrq = MRQ_UPHY;
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msg.tx.data = &req;
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msg.tx.size = sizeof(req);
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msg.rx.data = &resp;
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msg.rx.size = sizeof(resp);
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return tegra_bpmp_transfer(pcie_dev->bpmp, &msg);
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}
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static int uphy_bpmp_pcie_set_pll_state(int controller, int enable)
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{
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#define MAX_DEV_NAME_LEN 32
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char dev_name[MAX_DEV_NAME_LEN];
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struct mods_smmu_dev *smmu_pdev = NULL;
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int smmudev_idx, n;
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memset(dev_name, 0, MAX_DEV_NAME_LEN);
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n = snprintf(dev_name, MAX_DEV_NAME_LEN, "mods_pcie%d", controller);
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if (n < 0 || n >= MAX_DEV_NAME_LEN)
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return -EINVAL;
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smmudev_idx = get_mods_smmu_device_index(dev_name);
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if (smmudev_idx >= 0)
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smmu_pdev = get_mods_smmu_device(smmudev_idx);
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if (!smmu_pdev || smmudev_idx < 0) {
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mods_error_printk("smmu device %s is not found\n", dev_name);
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return -ENODEV;
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}
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smmu_pdev->cid = controller;
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return tegra_pcie_bpmp_set_pll_state(smmu_pdev, enable);
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}
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#else
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static int uphy_bpmp_pcie_set_pll_state(int controller, int enable)
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{
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mods_error_printk("bpmp mrq api is not supported\n");
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return -ENODEV;
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}
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#endif
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int esc_mods_bpmp_init_pcie_ep_pll(
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struct mods_client *client,
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struct MODS_INIT_PCIE_EP_PLL *p
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)
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{
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return uphy_bpmp_pcie_set_pll_state(p->ep_id, 1);
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}
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