Viswanath L b16a07152b ASoC: tegra-alt: Update DMIC DCR coeff to POR ...

TEGRA210_DMIC_DCR_BIQUAD_0_COEF_4 is corrected to 0x0
(as per latest POR)

Bug 200134942
Bug 200078772

Change-Id: I628c2d3e18615df476b67761553762a23f1fe47e
Signed-off-by: Viswanath L <viswanathl@nvidia.com>
(cherry picked from commit eb36521b1c8d91a7760f684d43e65101762d8655)
Reviewed-on: http://git-master/r/802835
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ravindra Lokhande <rlokhande@nvidia.com>
GVS: Gerrit_Virtual_Submit

2022-09-29 15:30:21 +05:30

..

soc

ASoC: tegra-alt: Update DMIC DCR coeff to POR

2022-09-29 15:30:21 +05:30