mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
synced 2025-12-22 09:11:26 +03:00
b268d2ef29
In T124, the RX_REGISTER_FULL interrupt is cleared by reading the RX_REGISTER instead of writing to the INT_STAT register as before. Bug 1364229 Change-Id: Ib080a48910304553b0752a3ede55ab0d7653dd77 Signed-off-by: Ankita Garg <ankitag@nvidia.com> Reviewed-on: http://git-master/r/275982 Reviewed-on: http://git-master/r/1164137 (cherry picked from commit b890e7f50d3d032fc3ede4c4935fdf2c4501f063)
382 lines
11 KiB
C
382 lines
11 KiB
C
/*
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* drivers/misc/tegra-cec/tegra_cec.c
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*
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* Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/workqueue.h>
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#include <linux/ktime.h>
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#include <linux/wait.h>
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#include <linux/sched.h>
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#include <linux/fs.h>
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#include <linux/uaccess.h>
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#include <linux/platform_device.h>
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#include <linux/miscdevice.h>
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#include <mach/clk.h>
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#include "tegra_cec.h"
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int tegra_cec_open(struct inode *inode, struct file *file)
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{
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struct miscdevice *miscdev = file->private_data;
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struct tegra_cec *cec = container_of(miscdev,
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struct tegra_cec, misc_dev);
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dev_dbg(cec->dev, "%s\n", __func__);
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file->private_data = cec;
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return 0;
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}
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int tegra_cec_release(struct inode *inode, struct file *file)
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{
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struct tegra_cec *cec = file->private_data;
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dev_dbg(cec->dev, "%s\n", __func__);
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return 0;
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}
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ssize_t tegra_cec_write(struct file *file, const char __user *buffer,
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size_t count, loff_t *ppos)
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{
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struct tegra_cec *cec = file->private_data;
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unsigned long write_buff;
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count = 4;
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if (copy_from_user(&write_buff, buffer, count))
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return -EFAULT;
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writel((TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY |
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TEGRA_CEC_INT_MASK_TX_REGISTER_UNDERRUN |
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TEGRA_CEC_INT_MASK_TX_FRAME_OR_BLOCK_NAKD |
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TEGRA_CEC_INT_MASK_TX_ARBITRATION_FAILED |
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TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED |
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TEGRA_CEC_INT_MASK_RX_REGISTER_FULL |
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TEGRA_CEC_INT_MASK_RX_REGISTER_OVERRUN),
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cec->cec_base + TEGRA_CEC_INT_MASK);
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wait_event_interruptible(cec->tx_waitq, cec->tx_wake == 1);
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writel(write_buff, cec->cec_base + TEGRA_CEC_TX_REGISTER);
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cec->tx_wake = 0;
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writel((TEGRA_CEC_INT_MASK_TX_REGISTER_UNDERRUN |
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TEGRA_CEC_INT_MASK_TX_FRAME_OR_BLOCK_NAKD |
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TEGRA_CEC_INT_MASK_TX_ARBITRATION_FAILED |
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TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED |
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TEGRA_CEC_INT_MASK_RX_REGISTER_FULL |
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TEGRA_CEC_INT_MASK_RX_REGISTER_OVERRUN),
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cec->cec_base + TEGRA_CEC_INT_MASK);
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write_buff = 0x00;
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return count;
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}
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ssize_t tegra_cec_read(struct file *file, char __user *buffer,
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size_t count, loff_t *ppos)
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{
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struct tegra_cec *cec = file->private_data;
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count = 2;
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if (cec->rx_wake == 0)
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if (file->f_flags & O_NONBLOCK)
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return -EAGAIN;
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wait_event_interruptible(cec->rx_waitq, cec->rx_wake == 1);
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if (copy_to_user(buffer, &(cec->rx_buffer), count))
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return -EFAULT;
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cec->rx_buffer = 0x0;
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cec->rx_wake = 0;
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return count;
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}
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static irqreturn_t tegra_cec_irq_handler(int irq, void *data)
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{
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struct device *dev = data;
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struct tegra_cec *cec = dev_get_drvdata(dev);
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unsigned long status;
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status = readl(cec->cec_base + TEGRA_CEC_INT_STAT);
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if (!status)
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return IRQ_HANDLED;
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if ((status & TEGRA_CEC_INT_STAT_RX_REGISTER_OVERRUN) ||
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(status & TEGRA_CEC_INT_STAT_RX_BUS_ANOMALY_DETECTED) ||
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(status & TEGRA_CEC_INT_STAT_RX_START_BIT_DETECTED) ||
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(status & TEGRA_CEC_INT_STAT_RX_BUS_ERROR_DETECTED)) {
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writel((TEGRA_CEC_INT_STAT_RX_REGISTER_OVERRUN |
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TEGRA_CEC_INT_STAT_RX_BUS_ANOMALY_DETECTED |
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TEGRA_CEC_INT_STAT_RX_START_BIT_DETECTED |
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TEGRA_CEC_INT_STAT_RX_BUS_ERROR_DETECTED),
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cec->cec_base + TEGRA_CEC_INT_STAT);
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} else if (status & TEGRA_CEC_INT_STAT_RX_REGISTER_FULL) {
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writel((TEGRA_CEC_INT_STAT_RX_REGISTER_FULL),
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cec->cec_base + TEGRA_CEC_INT_STAT);
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cec->rx_buffer = readw(cec->cec_base + TEGRA_CEC_RX_REGISTER);
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cec->rx_wake = 1;
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wake_up_interruptible(&cec->rx_waitq);
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} else if ((status & TEGRA_CEC_INT_STAT_TX_REGISTER_UNDERRUN) ||
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(status & TEGRA_CEC_INT_STAT_TX_FRAME_OR_BLOCK_NAKD) ||
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(status & TEGRA_CEC_INT_STAT_TX_ARBITRATION_FAILED) ||
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(status & TEGRA_CEC_INT_STAT_TX_BUS_ANOMALY_DETECTED)) {
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writel((TEGRA_CEC_INT_STAT_TX_REGISTER_UNDERRUN |
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TEGRA_CEC_INT_STAT_TX_FRAME_OR_BLOCK_NAKD |
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TEGRA_CEC_INT_STAT_TX_REGISTER_EMPTY |
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TEGRA_CEC_INT_STAT_TX_ARBITRATION_FAILED |
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TEGRA_CEC_INT_STAT_TX_BUS_ANOMALY_DETECTED),
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cec->cec_base + TEGRA_CEC_INT_STAT);
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} else if (status & TEGRA_CEC_INT_STAT_TX_REGISTER_EMPTY) {
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cec->tx_wake = 1;
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wake_up_interruptible(&cec->tx_waitq);
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writel((TEGRA_CEC_INT_STAT_TX_REGISTER_EMPTY),
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cec->cec_base + TEGRA_CEC_INT_STAT);
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} else if (status & TEGRA_CEC_INT_STAT_TX_FRAME_TRANSMITTED) {
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writel((TEGRA_CEC_INT_STAT_TX_FRAME_TRANSMITTED),
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cec->cec_base + TEGRA_CEC_INT_STAT);
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}
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return IRQ_HANDLED;
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}
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static const struct file_operations tegra_cec_fops = {
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.owner = THIS_MODULE,
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.open = tegra_cec_open,
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.release = tegra_cec_release,
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.read = tegra_cec_read,
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.write = tegra_cec_write,
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};
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static void tegra_cec_init(struct tegra_cec *cec)
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{
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writel(0x00, cec->cec_base + TEGRA_CEC_HW_CONTROL);
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writel(0x00, cec->cec_base + TEGRA_CEC_INT_MASK);
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writel(0xffffffff, cec->cec_base + TEGRA_CEC_INT_STAT);
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msleep(1000);
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writel(0x00, cec->cec_base + TEGRA_CEC_SW_CONTROL);
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writel(((TEGRA_CEC_LOGICAL_ADDR<<TEGRA_CEC_HW_CONTROL_RX_LOGICAL_ADDRS_MASK)&
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(~TEGRA_CEC_HW_CONTROL_RX_SNOOP) &
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(~TEGRA_CEC_HW_CONTROL_RX_NAK_MODE) &
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(~TEGRA_CEC_HW_CONTROL_TX_NAK_MODE) &
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(~TEGRA_CEC_HW_CONTROL_FAST_SIM_MODE)) |
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(TEGRA_CEC_HW_CONTROL_TX_RX_MODE),
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cec->cec_base + TEGRA_CEC_HW_CONTROL);
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writel(0x00, cec->cec_base + TEGRA_CEC_INPUT_FILTER);
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writel((0x7a << TEGRA_CEC_RX_TIMING_0_RX_START_BIT_MAX_LO_TIME_MASK) |
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(0x6d << TEGRA_CEC_RX_TIMING_0_RX_START_BIT_MIN_LO_TIME_MASK) |
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(0x93 << TEGRA_CEC_RX_TIMING_0_RX_START_BIT_MAX_DURATION_MASK) |
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(0x86 << TEGRA_CEC_RX_TIMING_0_RX_START_BIT_MIN_DURATION_MASK),
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cec->cec_base + TEGRA_CEC_RX_TIMING_0);
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writel((0x35 << TEGRA_CEC_RX_TIMING_1_RX_DATA_BIT_MAX_LO_TIME_MASK) |
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(0x21 << TEGRA_CEC_RX_TIMING_1_RX_DATA_BIT_SAMPLE_TIME_MASK) |
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(0x56 << TEGRA_CEC_RX_TIMING_1_RX_DATA_BIT_MAX_DURATION_MASK) |
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(0x40 << TEGRA_CEC_RX_TIMING_1_RX_DATA_BIT_MIN_DURATION_MASK),
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cec->cec_base + TEGRA_CEC_RX_TIMING_1);
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writel((0x50 << TEGRA_CEC_RX_TIMING_2_RX_END_OF_BLOCK_TIME_MASK),
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cec->cec_base + TEGRA_CEC_RX_TIMING_2);
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writel((0x74 << TEGRA_CEC_TX_TIMING_0_TX_START_BIT_LO_TIME_MASK) |
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(0x8d << TEGRA_CEC_TX_TIMING_0_TX_START_BIT_DURATION_MASK) |
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(0x08 << TEGRA_CEC_TX_TIMING_0_TX_BUS_XITION_TIME_MASK) |
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(0x71 << TEGRA_CEC_TX_TIMING_0_TX_BUS_ERROR_LO_TIME_MASK),
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cec->cec_base + TEGRA_CEC_TX_TIMING_0);
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writel((0x2f << TEGRA_CEC_TX_TIMING_1_TX_LO_DATA_BIT_LO_TIME_MASK) |
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(0x13 << TEGRA_CEC_TX_TIMING_1_TX_HI_DATA_BIT_LO_TIME_MASK) |
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(0x4b << TEGRA_CEC_TX_TIMING_1_TX_DATA_BIT_DURATION_MASK) |
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(0x21 << TEGRA_CEC_TX_TIMING_1_TX_ACK_NAK_BIT_SAMPLE_TIME_MASK),
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cec->cec_base + TEGRA_CEC_TX_TIMING_1);
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writel((0x07 << TEGRA_CEC_TX_TIMING_2_BUS_IDLE_TIME_ADDITIONAL_FRAME_MASK) |
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(0x05 << TEGRA_CEC_TX_TIMING_2_TX_BUS_IDLE_TIME_NEW_FRAME_MASK) |
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(0x03 << TEGRA_CEC_TX_TIMING_2_TX_BUS_IDLE_TIME_RETRY_FRAME_MASK),
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cec->cec_base + TEGRA_CEC_TX_TIMING_2);
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writel((TEGRA_CEC_INT_MASK_TX_REGISTER_UNDERRUN |
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TEGRA_CEC_INT_MASK_TX_FRAME_OR_BLOCK_NAKD |
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TEGRA_CEC_INT_MASK_TX_ARBITRATION_FAILED |
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TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED |
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TEGRA_CEC_INT_MASK_RX_REGISTER_FULL |
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TEGRA_CEC_INT_MASK_RX_REGISTER_OVERRUN),
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cec->cec_base + TEGRA_CEC_INT_MASK);
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}
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static int __devinit tegra_cec_probe(struct platform_device *pdev)
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{
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struct tegra_cec *cec;
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struct resource *res;
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int ret = 0;
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cec = devm_kzalloc(&pdev->dev, sizeof(struct tegra_cec), GFP_KERNEL);
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if (!cec)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&pdev->dev,
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"Unable to allocate resources for device.\n");
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ret = -EBUSY;
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goto cec_error;
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}
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if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
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pdev->name)) {
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dev_err(&pdev->dev,
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"Unable to request mem region for device.\n");
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ret = -EBUSY;
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goto cec_error;
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}
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cec->tegra_cec_irq = platform_get_irq(pdev, 0);
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if (cec->tegra_cec_irq <= 0) {
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ret = -EBUSY;
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goto cec_error;
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}
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cec->cec_base = devm_ioremap_nocache(&pdev->dev, res->start,
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resource_size(res));
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if (!cec->cec_base) {
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dev_err(&pdev->dev, "Unable to grab IOs for device.\n");
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ret = -EBUSY;
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goto cec_error;
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}
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cec->clk = clk_get(&pdev->dev, "cec");
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if (IS_ERR_OR_NULL(cec->clk)) {
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dev_err(&pdev->dev, "can't get clock for CEC\n");
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ret = -ENOENT;
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goto clk_error;
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}
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clk_enable(cec->clk);
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/* set context info. */
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cec->dev = &pdev->dev;
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cec->rx_wake = 0;
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cec->tx_wake = 0;
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init_waitqueue_head(&cec->rx_waitq);
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init_waitqueue_head(&cec->tx_waitq);
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platform_set_drvdata(pdev, cec);
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/* clear out the hardware. */
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tegra_cec_init(cec);
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device_init_wakeup(&pdev->dev, 1);
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cec->misc_dev.minor = MISC_DYNAMIC_MINOR;
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cec->misc_dev.name = TEGRA_CEC_NAME;
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cec->misc_dev.fops = &tegra_cec_fops;
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cec->misc_dev.parent = &pdev->dev;
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if (misc_register(&cec->misc_dev)) {
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printk(KERN_WARNING "Couldn't register device , %s.\n", TEGRA_CEC_NAME);
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goto cec_error;
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}
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ret = devm_request_irq(&pdev->dev, cec->tegra_cec_irq,
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tegra_cec_irq_handler, IRQF_DISABLED, "cec_irq", &pdev->dev);
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if (ret) {
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dev_err(&pdev->dev,
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"Unable to request interrupt for device (err=%d).\n", ret);
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goto cec_error;
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}
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dev_notice(&pdev->dev, "probed\n");
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return 0;
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cec_error:
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clk_disable(cec->clk);
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clk_put(cec->clk);
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clk_error:
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return ret;
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}
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static int tegra_cec_remove(struct platform_device *pdev)
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{
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struct tegra_cec *cec = platform_get_drvdata(pdev);
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clk_disable(cec->clk);
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clk_put(cec->clk);
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misc_deregister(&cec->misc_dev);
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return 0;
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}
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#ifdef CONFIG_PM
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static int tegra_cec_suspend(struct platform_device *pdev, pm_message_t state)
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{
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struct tegra_cec *cec = platform_get_drvdata(pdev);
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clk_disable(cec->clk);
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return 0;
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}
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static int tegra_cec_resume(struct platform_device *pdev)
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{
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struct tegra_cec *cec = platform_get_drvdata(pdev);
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clk_enable(cec->clk);
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tegra_cec_init(cec);
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return 0;
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}
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#endif
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static struct platform_driver tegra_cec_driver = {
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.driver = {
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.name = TEGRA_CEC_NAME,
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.owner = THIS_MODULE,
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},
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.probe = tegra_cec_probe,
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.remove = tegra_cec_remove,
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#ifdef CONFIG_PM
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.suspend = tegra_cec_suspend,
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.resume = tegra_cec_resume,
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#endif
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};
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module_platform_driver(tegra_cec_driver);
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