mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
synced 2025-12-22 09:11:26 +03:00
2e8de96526
Add helper code for booting RISC-V based engines where firmware is located in a carveout. Bug 3778105 Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Change-Id: I36eda4774838fc73098bcf2eff8c3f1983c82465 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2771768 (cherry picked from commit cc6935ec1dc1e6557f5e0a7d53ef9f0c3ff12fb3) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2759060 Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com> Tested-by: Jonathan Hunter <jonathanh@nvidia.com>
31 lines
694 B
C
31 lines
694 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
/*
|
|
* Copyright (c) 2022, NVIDIA Corporation.
|
|
*/
|
|
|
|
#ifndef DRM_TEGRA_RISCV_H
|
|
#define DRM_TEGRA_RISCV_H
|
|
|
|
struct tegra_drm_riscv_descriptor {
|
|
u32 manifest_offset;
|
|
u32 code_offset;
|
|
u32 code_size;
|
|
u32 data_offset;
|
|
u32 data_size;
|
|
};
|
|
|
|
struct tegra_drm_riscv {
|
|
/* User initializes */
|
|
struct device *dev;
|
|
void __iomem *regs;
|
|
|
|
struct tegra_drm_riscv_descriptor bl_desc;
|
|
struct tegra_drm_riscv_descriptor os_desc;
|
|
};
|
|
|
|
int tegra_drm_riscv_read_descriptors(struct tegra_drm_riscv *riscv);
|
|
int tegra_drm_riscv_boot_bootrom(struct tegra_drm_riscv *riscv, phys_addr_t image_address,
|
|
u32 gscid, const struct tegra_drm_riscv_descriptor *desc);
|
|
|
|
#endif
|