mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
synced 2025-12-22 17:25:35 +03:00
b4955d4ea6
commit b4bc1cf56020("ASoC: tegra-alt: Avoid reg access after shutdown")
avoided device register access after shutdown() has been called. This
otherwise resulted in occasional SError and resulted in crash. The reason
for this was runtime PM does not work after shutdown and it was seen on
vK4.4
Looks like the issue has been fixed from vK4.5 onwards, where PM domain
detach is avoided during shutdown. Following is the upstream commmit.
"platform: Do not detach from PM domains on shutdown"
Bug 200503387
Change-Id: I5f3d18f05e434d5a1ed5b597362a39ec9a9f010b
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2161809
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
184 lines
8.8 KiB
C
184 lines
8.8 KiB
C
/*
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* tegra186_dspk_alt.h - Definitions for Tegra186 DSPK driver
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*
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* Copyright (c) 2015-2019 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __TEGRA186_DSPK_ALT_H__
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#define __TEGRA186_DSPK_ALT_H__
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/* Register offsets from DSPK BASE */
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#define TEGRA186_DSPK_AXBAR_RX_STATUS 0x0c
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#define TEGRA186_DSPK_AXBAR_RX_INT_STATUS 0x10
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#define TEGRA186_DSPK_AXBAR_RX_INT_MASK 0x14
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#define TEGRA186_DSPK_AXBAR_RX_INT_SET 0x18
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#define TEGRA186_DSPK_AXBAR_RX_INT_CLEAR 0x1c
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#define TEGRA186_DSPK_AXBAR_RX_CIF_CTRL 0x20
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#define TEGRA186_DSPK_AXBAR_RX_CYA 0x24
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#define TEGRA186_DSPK_AXBAR_RX_CIF_FIFO_STATUS 0x28
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#define TEGRA186_DSPK_ENABLE 0x40
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#define TEGRA186_DSPK_SOFT_RESET 0x44
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#define TEGRA186_DSPK_CG 0x48
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#define TEGRA186_DSPK_STATUS 0x4c
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#define TEGRA186_DSPK_INT_STATUS 0x50
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#define TEGRA186_DSPK_CORE_CTRL 0x60
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#define TEGRA186_DSPK_CODEC_CTRL 0x64
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#define TEGRA186_DSPK_CODEC_DATA 0x68
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#define TEGRA186_DSPK_CODEC_ENABLE 0x6c
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#define TEGRA186_DSPK_CLK_TRIM 0x70
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#define TEGRA186_DSPK_SDM_COEF_A_2 0x74
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#define TEGRA186_DSPK_SDM_COEF_A_3 0x78
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#define TEGRA186_DSPK_SDM_COEF_A_4 0x7c
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#define TEGRA186_DSPK_SDM_COEF_A_5 0x80
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#define TEGRA186_DSPK_SDM_COEF_C_1 0x84
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#define TEGRA186_DSPK_SDM_COEF_C_2 0x88
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#define TEGRA186_DSPK_SDM_COEF_C_3 0x8c
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#define TEGRA186_DSPK_SDM_COEF_C_4 0x90
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#define TEGRA186_DSPK_SDM_COEF_G_1 0x94
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#define TEGRA186_DSPK_SDM_COEF_G_2 0x98
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#define TEGRA186_DSPK_DEBUG_STATUS 0x9c
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#define TEGRA186_DSPK_DEBUG_CIF_CNTR 0xa0
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#define TEGRA186_DSPK_DEBUG_STAGE1_CNTR 0xa4
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#define TEGRA186_DSPK_DEBUG_STAGE2_CNTR 0xa8
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#define TEGRA186_DSPK_DEBUG_STAGE3_CNTR 0xac
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#define TEGRA186_DSPK_DEBUG_STAGE4_CNTR 0xb0
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/* Constants for DSPK */
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#define TEGRA186_DSPK_OSR_32 0
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#define TEGRA186_DSPK_OSR_64 1
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#define TEGRA186_DSPK_OSR_128 2
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#define TEGRA186_DSPK_OSR_256 3
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/* DSPK ENABLE Register field */
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#define TEGRA186_DSPK_ENABLE_EN BIT(0)
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/* DSPK SOFT RESET field */
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#define TEGRA186_DSPK_SOFT_RESET_EN BIT(0)
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/* DSPK CG field */
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#define TEGRA186_DSPK_CG_SLCG_EN BIT(0)
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/* DSPK STATUS fields */
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#define TEGRA186_DSPK_CODEC_CONFIG_DONE_SHIFT 14
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#define TEGRA186_DSPK_CODEC_CONFIG_DONE_MASK (0x1 << TEGRA186_DSPK_CODEC_CONFIG_DONE_SHIFT)
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#define TEGRA186_DSPK_SLCG_CLKEN_SHIFT 12
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#define TEGRA186_DSPK_SLCG_CLKEN_MASK (0x1 << TEGRA186_DSPK_SLCG_CLKEN_SHIFT)
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#define TEGRA186_DSPK_RX_CIF_FULL_SHIFT 10
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#define TEGRA186_DSPK_RX_CIF_FULL_MASK (0x1 << TEGRA186_DSPK_RX_CIF_FULL_SHIFT)
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#define TEGRA186_DSPK_RX_CIF_EMPTY_SHIFT 9
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#define TEGRA186_DSPK_RX_CIF_EMPTY_MASK (0x1 << TEGRA186_DSPK_RX_CIF_EMPTY_SHIFT)
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#define TEGRA186_DSPK_RX_ENABLED_SHIFT 8
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#define TEGRA186_DSPK_RX_ENABLED_MASK (0x1 << TEGRA186_DSPK_RX_ENABLED_SHIFT)
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/* DSPK INT STATUS fields */
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#define TEGRA186_DSPK_INT_CODEC_CONFIG_DONE_SHIFT 12
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#define TEGRA186_DSPK_INT_CODEC_CONFIG_DONE_MASK (0x1 << TEGRA186_DSPK_INT_CODEC_CONFIG_DONE_SHIFT)
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#define TEGRA186_DSPK_RX_CIF_FIFO_UNDERRUN_SHIFT 9
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#define TEGRA186_DSPK_RX_CIF_FIFO_UNDERRUN_MASK (0x1 << TEGRA186_DSPK_RX_CIF_FIFO_UNDERRUN_SHIFT)
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#define TEGRA186_DSPK_RX_DONE_SHIFT 8
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#define TEGRA186_DSPK_RX_DONE_MASK (0x1 << TEGRA186_DSPK_RX_DONE_SHIFT)
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/* DSPK CORE CONTROL fields */
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#define TEGRA186_DSPK_GAIN1_SHIFT 28
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#define TEGRA186_DSPK_GAIN1_MASK (0x7 << TEGRA186_DSPK_GAIN1_SHIFT)
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#define TEGRA186_DSPK_GAIN2_SHIFT 24
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#define TEGRA186_DSPK_GAIN2_MASK (0x7 << TEGRA186_DSPK_GAIN2_SHIFT)
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#define TEGRA186_DSPK_GAIN3_SHIFT 20
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#define TEGRA186_DSPK_GAIN3_MASK (0x7 << TEGRA186_DSPK_GAIN3_SHIFT)
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#define TEGRA186_DSPK_FILTER_MODE_SHIFT 16
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#define TEGRA186_DSPK_FILTER_MODE_MASK (0x1 << TEGRA186_DSPK_FILTER_MODE_SHIFT)
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#define TEGRA186_DSPK_CHANNEL_SELECT_SHIFT 8
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#define TEGRA186_DSPK_CHANNEL_SELECT_MASK (0x3 << TEGRA186_DSPK_CHANNEL_SELECT_SHIFT)
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#define TEGRA186_DSPK_OSR_SHIFT 4
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#define TEGRA186_DSPK_OSR_MASK (0x3 << TEGRA186_DSPK_OSR_SHIFT)
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#define TEGRA186_DSPK_LRSEL_POLARITY_SHIFT 0
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#define TEGRA186_DSPK_LRSEL_POLARITY_MASK (0x1 << TEGRA186_DSPK_LRSEL_POLARITY_SHIFT)
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/* DSPK CODEC CONTROL fileds */
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#define TEGRA186_DSPK_CODEC_CHANNEL_SELECT_SHIFT 24
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#define TEGRA186_DSPK_CODEC_CHANNEL_SELECT_MASK (0x3 << TEGRA186_DSPK_CODEC_CHANNEL_SELECT_SHIFT)
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#define TEGRA186_DSPK_CODEC_BIT_ORDER_SHIFT 16
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#define TEGRA186_DSPK_CODEC_BIT_MASK (0x1 << TEGRA186_DSPK_CODEC_BIT_ORDER_SHIFT)
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#define TEGRA186_DSPK_CODEC_CONFIG_MODE_SHIFT 12
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#define TEGRA186_DSPK_CODEC_CONFIG_MODE_MASK (0x1 << TEGRA186_DSPK_CODEC_CONFIG_MODE_SHIFT)
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#define TEGRA186_DSPK_CODEC_CONFIG_REP_NUM_SHIFT 0
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#define TEGRA186_DSPK_CODEC_CONFIG_REP_NUM_MASK (0xff << TEGRA186_DSPK_CODEC_CONFIG_REP_NUM_SHIFT)
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/* DSPK CODEC ENABLE fields */
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#define TEGRA186_DSPK_CODEC_ENABLE_SHIFT 0
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#define TEGRA186_DSPK_CODEC_ENABLE_MASK (0x1 << TEGRA186_DSPK_CODEC_ENABLE_SHIFT)
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/* DSPL CLK TRIM field */
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#define TEGRA186_DSPK_CLK_TRIM_SHIFT 0
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#define TEGRA186_DSPK_CLK_TRIM_MASK (0x1f << TEGRA186_DSPK_CLK_TRIM_SHIFT)
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/* DSPK DEBUG Register fields*/
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#define TEGRA186_DSPK_DEBUG_STATUS_SHIFT 0
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#define TEGRA186_DSPK_DEBUG_STATUS_MASK (0xff << TEGRA186_DSPK_DEBUG_STATUS_SHIFT)
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#define TEGRA186_DSPK_DEBUG_CIF_CH0_SHIFT 16
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#define TEGRA186_DSPK_DEBUG_CIF_CH0_MASK (0xffff << TEGRA186_DSPK_DEBUG_CIF_CH0_SHIFT)
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#define TEGRA186_DSPK_DEBUG_CIF_CH1_SHIFT 0
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#define TEGRA186_DSPK_DEBUG_CIF_CH1_MASK (0xffff << TEGRA186_DSPK_DEBUG_CIF_CH1_SHIFT)
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#define TEGRA186_DSPK_DEBUG_STAGE1_CH0_SHIFT 16
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#define TEGRA186_DSPK_DEBUG_STAGE1_CH0_MASK (0xffff << TEGRA186_DSPK_DEBUG_STAGE1_CH0_SHIFT)
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#define TEGRA186_DSPK_DEBUG_STAGE1_CH1_SHIFT 0
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#define TEGRA186_DSPK_DEBUG_STAGE1_CH1_MASK (0xffff << TEGRA186_DSPK_DEBUG_STAGE1_CH1_SHIFT)
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#define TEGRA186_DSPK_DEBUG_STAGE2_CH0_SHIFT 16
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#define TEGRA186_DSPK_DEBUG_STAGE2_CH0_MASK (0xffff << TEGRA186_DSPK_DEBUG_STAGE2_CH0_SHIFT)
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#define TEGRA186_DSPK_DEBUG_STAGE2_CH1_SHIFT 0
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#define TEGRA186_DSPK_DEBUG_STAGE2_CH1_MASK (0xffff << TEGRA186_DSPK_DEBUG_STAGE2_CH1_SHIFT)
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#define TEGRA186_DSPK_DEBUG_STAGE3_CH0_SHIFT 16
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#define TEGRA186_DSPK_DEBUG_STAGE3_CH0_MASK (0xffff << TEGRA186_DSPK_DEBUG_STAGE3_CH0_SHIFT)
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#define TEGRA186_DSPK_DEBUG_STAGE3_CH1_SHIFT 0
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#define TEGRA186_DSPK_DEBUG_STAGE3_CH1_MASK (0xffff << TEGRA186_DSPK_DEBUG_STAGE3_CH1_SHIFT)
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#define TEGRA186_DSPK_DEBUG_STAGE4_CH0_SHIFT 16
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#define TEGRA186_DSPK_DEBUG_STAGE4_CH0_MASK (0xffff << TEGRA186_DSPK_DEBUG_STAGE4_CH0_SHIFT)
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#define TEGRA186_DSPK_DEBUG_STAGE4_CH1_SHIFT 0
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#define TEGRA186_DSPK_DEBUG_STAGE4_CH1_MASK (0xffff << TEGRA186_DSPK_DEBUG_STAGE4_CH1_SHIFT)
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#define TEGRA186_DSPK_RX_FIFO_DEPTH 4
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struct tegra186_dspk {
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struct clk *clk_dspk;
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struct clk *clk_pll_a_out0;
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struct regmap *regmap;
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const char *prod_name;
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unsigned int rx_fifo_th; /* threshold in terms of frames */
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unsigned int osr_val; /* osr value */
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};
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#endif
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