mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
synced 2025-12-25 10:42:21 +03:00
14c6de030c
Jira ESDP-28694 Change-Id: Ic6fa743f34b6331d85334465961ae64a91aee588 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3307869 GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Mark Mendez <mmendez@nvidia.com>
549 lines
20 KiB
YAML
549 lines
20 KiB
YAML
# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms and conditions of the GNU General Public License,
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# version 2, as published by the Free Software Foundation.
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#
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# This program is distributed in the hope it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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# more details.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display@8808c00000/nvidia,tegra264-display.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Nvidia Tegra Display Driver
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maintainers:
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- Mihir Pradeep Garude
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description: |
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The following nodes use this compatibility
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- /display@8808c00000
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select:
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properties:
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compatible:
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minItems: 1
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maxItems: 1
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items:
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enum:
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- nvidia,tegra264-display
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required:
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- compatible
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properties:
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power-domains:
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$ref: "/schemas/types.yaml#/definitions/uint32-matrix"
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items:
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minItems: 2
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maxItems: 2
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items:
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0x1
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maximum: 0x1
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nvidia,num-dpaux-instance:
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$ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0x4
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maximum: 0x4
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nvidia,bpmp:
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$ref: "/schemas/types.yaml#/definitions/uint32"
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reg-names:
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$ref: "/schemas/types.yaml#/definitions/string-array"
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items:
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enum:
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- nvdisplay
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- dpaux0
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- hdacodec
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- mipical
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- vdisp
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reg:
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$ref: "/schemas/types.yaml#/definitions/uint32-matrix"
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description: |
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Registers are given by a tuple of two values:
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- register address:
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- register block size.
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items:
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minItems: 4
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maxItems: 4
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items:
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0x81
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maximum: 0x88
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0x8c00000
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maximum: 0x89840000
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0x0
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maximum: 0x0
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0xfff
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maximum: 0x1fffff
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interrupt-names:
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$ref: "/schemas/types.yaml#/definitions/string-array"
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items:
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enum:
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- nvdisplay
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- dpaux0
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- dpaux1
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- dpaux2
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- dpaux3
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- hdacodec
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- vdisp
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interrupts:
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$ref: "/schemas/types.yaml#/definitions/uint32-matrix"
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description: |
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Interrupts are give by a tuple of 3 values:
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- interrupt specifier (GIC_SPI = 0, GIC_PPI = 1)
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definitions in dt-bindings/interrupt-controller/arm-gic.h
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- interrupt number
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- trigger type (rising edge, falling edge, both, etc)
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definitions in dt-bindings/interrupt-controller/irq.h
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items:
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items:
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0x0
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maximum: 0x0
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0xf7
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maximum: 0x101
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0x4
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maximum: 0x4
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clocks:
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$ref: "/schemas/types.yaml#/definitions/uint32-matrix"
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description: |
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Clocks are given by a tuple of 2 values:
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- Phandle to the device
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- Clock ID
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items:
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minItems: 2
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maxItems: 2
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items:
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0x1
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maximum: 0x1d3
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clock-names:
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$ref: "/schemas/types.yaml#/definitions/string-array"
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items:
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enum:
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- nvdisplayhub_clk
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- nvdisplay_disp_clk
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- nvdisplay_p0_clk
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- nvdisplay_p1_clk
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- nvdisplay_p2_clk
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- nvdisplay_p3_clk
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- nvdisplay_p4_clk
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- nvdisplay_p5_clk
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- nvdisplay_p6_clk
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- nvdisplay_p7_clk
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- fuse_clk
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- sppll0_clkouta_clk
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- sppll0_clkoutb_clk
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- sppll0_clkoutpn_clk
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- sppll1_clkoutpn_clk
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- sppll0_div27_clk
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- sppll1_div27_clk
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- vpll0_clk
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- vpll1_clk
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- vpll2_clk
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- vpll3_clk
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- vpll4_clk
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- vpll5_clk
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- vpll6_clk
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- vpll7_clk
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- rg0_clk
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- rg1_clk
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- rg2_clk
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- rg3_clk
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- rg4_clk
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- rg5_clk
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- rg6_clk
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- rg7_clk
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- disppll_clk
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- pre_sor0_clk
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- pre_sor1_clk
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- pre_sor2_clk
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- pre_sor3_clk
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- dp_link_ref_clk
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- dp_linkb_ref_clk
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- dp_linkc_ref_clk
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- dp_linkd_ref_clk
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- sor_linka_input_clk
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- sor_linkb_input_clk
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- sor_linkc_input_clk
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- sor_linkd_input_clk
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- sor_linka_afifo_clk
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- sor_linkb_afifo_clk
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- sor_linkc_afifo_clk
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- sor_linkd_afifo_clk
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- sor0_clk
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- sor1_clk
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- sor2_clk
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- sor3_clk
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- sor_pad_input_clk
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- sor_padb_input_clk
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- sor_padc_input_clk
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- sor_padd_input_clk
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- sor0_pad_clk
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- sor1_pad_clk
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- sor2_pad_clk
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- sor3_pad_clk
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- sf0_clk
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- sf1_clk
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- sf2_clk
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- sf3_clk
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- sf4_clk
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- sf5_clk
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- sf6_clk
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- sf7_clk
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- sor0_ref_pll_clk
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- sor1_ref_pll_clk
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- sor2_ref_pll_clk
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- sor3_ref_pll_clk
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- sor0_ref_clk
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- sor1_ref_clk
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- sor2_ref_clk
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- sor3_ref_clk
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- osc_clk
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- dsc_clk
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- maud_clk
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- aza_2xbit_clk
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- disp_root
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- vpllx_sor0_muxed_clk
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- vpllx_sor1_muxed_clk
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- vpllx_sor2_muxed_clk
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- vpllx_sor3_muxed_clk
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- sf0_sor_clk
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- sf1_sor_clk
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- sf2_sor_clk
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- sf3_sor_clk
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- sf4_sor_clk
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- sf5_sor_clk
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- sf6_sor_clk
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- sf7_sor_clk
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- dpaux0_clk
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- emc_clk
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nvidia,disp-sw-soc-chip-id:
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$ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0x2650
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maximum: 0x2650
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resets:
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$ref: "/schemas/types.yaml#/definitions/uint32-matrix"
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description: |
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Resets are given by a tuple of 2 values:
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- Phandle to the device
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- Reset ID
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items:
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minItems: 2
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maxItems: 2
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items:
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0x8
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maximum: 0x1f
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reset-names:
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$ref: "/schemas/types.yaml#/definitions/string-array"
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items:
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enum:
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- dpaux0_reset
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- hdacodec_reset
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interconnects:
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$ref: "/schemas/types.yaml#/definitions/uint32-matrix"
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items:
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minItems: 3
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maxItems: 3
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items:
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0x182
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maximum: 0x182
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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interconnect-names:
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$ref: "/schemas/types.yaml#/definitions/string-array"
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items:
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enum:
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- read-1
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iommus:
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$ref: "/schemas/types.yaml#/definitions/uint32-matrix"
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description: |
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iommus are given by a tuple of 2 values:
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- Phandle to the device
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- Device ID
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items:
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minItems: 2
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maxItems: 2
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items:
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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- $ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0x900
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maximum: 0x900
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non-coherent:
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$ref: "/schemas/types.yaml#/definitions/flag"
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single_stage_iso_smmu:
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$ref: "/schemas/types.yaml#/definitions/flag"
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required:
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- compatible
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- reg
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- interrupt-names
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- interrupts
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- clocks
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- clock-names
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- resets
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- reset-names
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- iommus
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examples:
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- |
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display@8808c00000 {
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compatible = "nvidia,tegra264-display";
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power-domains = <&bpmp TEGRA264_POWER_DOMAIN_DISP>;
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nvidia,num-dpaux-instance = <0x00000004>;
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nvidia,bpmp = <&bpmp>;
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reg-names = "nvdisplay, dpaux0, hdacodec, mipical, vdisp";
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reg = <0x88 0x8c00000 0x00 0x1fffff>,
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<0x88 0x9680000 0x00 0x7ffff>,
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<0x88 0x9101000 0x00 0xfff>,
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<0x81 0x89840000 0x00 0xffff>,
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<0x88 0x8d00000 0x00 0x00010000>;
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interrupt-names = "nvdisplay, dpaux0, dpaux1, dpaux2, dpaux3, hdacodec, vdisp";
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interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA264_CLK_HUB>,
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<&bpmp TEGRA264_CLK_DISP>,
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<&bpmp TEGRA264_CLK_RG0_DIV>,
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<&bpmp TEGRA264_CLK_RG1_DIV>,
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<&bpmp TEGRA264_CLK_RG2_DIV>,
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<&bpmp TEGRA264_CLK_RG3_DIV>,
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<&bpmp TEGRA264_CLK_RG4_DIV>,
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<&bpmp TEGRA264_CLK_RG5_DIV>,
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<&bpmp TEGRA264_CLK_RG6_DIV>,
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<&bpmp TEGRA264_CLK_RG7_DIV>,
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<&bpmp TEGRA264_CLK_FUSE>,
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<&bpmp TEGRA264_CLK_SPPLL0_CLKOUT1A>,
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<&bpmp TEGRA264_CLK_SPPLL0_CLKOUT2A>,
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<&bpmp TEGRA264_CLK_SPPLL0_CLKOUT270>,
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<&bpmp TEGRA264_CLK_SPPLL1_CLKOUT270>,
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<&bpmp TEGRA264_CLK_SPPLL0_CLKOUT100>,
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<&bpmp TEGRA264_CLK_SPPLL1_CLKOUT100>,
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<&bpmp TEGRA264_CLK_VPLL0>,
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<&bpmp TEGRA264_CLK_VPLL1>,
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<&bpmp TEGRA264_CLK_VPLL2>,
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<&bpmp TEGRA264_CLK_VPLL3>,
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<&bpmp TEGRA264_CLK_VPLL4>,
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<&bpmp TEGRA264_CLK_VPLL5>,
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<&bpmp TEGRA264_CLK_VPLL6>,
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<&bpmp TEGRA264_CLK_VPLL7>,
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<&bpmp TEGRA264_CLK_RG0>,
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<&bpmp TEGRA264_CLK_RG1>,
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<&bpmp TEGRA264_CLK_RG2>,
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<&bpmp TEGRA264_CLK_RG3>,
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<&bpmp TEGRA264_CLK_RG4>,
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<&bpmp TEGRA264_CLK_RG5>,
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<&bpmp TEGRA264_CLK_RG6>,
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<&bpmp TEGRA264_CLK_RG7>,
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<&bpmp TEGRA264_CLK_DISPPLL>,
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<&bpmp TEGRA264_CLK_PRE_SOR0>,
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<&bpmp TEGRA264_CLK_PRE_SOR1>,
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<&bpmp TEGRA264_CLK_PRE_SOR2>,
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<&bpmp TEGRA264_CLK_PRE_SOR3>,
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<&bpmp TEGRA264_CLK_DP_LINKA_REF>,
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<&bpmp TEGRA264_CLK_DP_LINKB_REF>,
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<&bpmp TEGRA264_CLK_DP_LINKC_REF>,
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<&bpmp TEGRA264_CLK_DP_LINKD_REF>,
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<&bpmp TEGRA264_CLK_SOR_LINKA_INPUT>,
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<&bpmp TEGRA264_CLK_SOR_LINKB_INPUT>,
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<&bpmp TEGRA264_CLK_SOR_LINKC_INPUT>,
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<&bpmp TEGRA264_CLK_SOR_LINKD_INPUT>,
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<&bpmp TEGRA264_CLK_SOR_LINKA_AFIFO>,
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<&bpmp TEGRA264_CLK_SOR_LINKB_AFIFO>,
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<&bpmp TEGRA264_CLK_SOR_LINKC_AFIFO>,
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<&bpmp TEGRA264_CLK_SOR_LINKD_AFIFO>,
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<&bpmp TEGRA264_CLK_SOR0>,
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<&bpmp TEGRA264_CLK_SOR1>,
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<&bpmp TEGRA264_CLK_SOR2>,
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<&bpmp TEGRA264_CLK_SOR3>,
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<&bpmp TEGRA264_CLK_LINKA_SYM>,
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<&bpmp TEGRA264_CLK_LINKB_SYM>,
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<&bpmp TEGRA264_CLK_LINKC_SYM>,
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<&bpmp TEGRA264_CLK_LINKD_SYM>,
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<&bpmp TEGRA264_CLK_SOR0_PAD>,
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<&bpmp TEGRA264_CLK_SOR1_PAD>,
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<&bpmp TEGRA264_CLK_SOR2_PAD>,
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<&bpmp TEGRA264_CLK_SOR3_PAD>,
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<&bpmp TEGRA264_CLK_SF0>,
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<&bpmp TEGRA264_CLK_SF1>,
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<&bpmp TEGRA264_CLK_SF2>,
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<&bpmp TEGRA264_CLK_SF3>,
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<&bpmp TEGRA264_CLK_SF4>,
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<&bpmp TEGRA264_CLK_SF5>,
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<&bpmp TEGRA264_CLK_SF6>,
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<&bpmp TEGRA264_CLK_SF7>,
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<&bpmp TEGRA264_CLK_SOR0_PLL_REF>,
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<&bpmp TEGRA264_CLK_SOR1_PLL_REF>,
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<&bpmp TEGRA264_CLK_SOR2_PLL_REF>,
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<&bpmp TEGRA264_CLK_SOR3_PLL_REF>,
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<&bpmp TEGRA264_CLK_SOR0_REF>,
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<&bpmp TEGRA264_CLK_SOR1_REF>,
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<&bpmp TEGRA264_CLK_SOR2_REF>,
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<&bpmp TEGRA264_CLK_SOR3_REF>,
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<&bpmp TEGRA264_CLK_OSC>,
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<&bpmp TEGRA264_CLK_DSC>,
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<&bpmp TEGRA264_CLK_MAUD>,
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<&bpmp TEGRA264_CLK_AZA_2XBIT>,
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<&bpmp TEGRA264_CLK_DISP_ROOT>,
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<&bpmp TEGRA264_CLK_VPLLX_SOR0_MUXED>,
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<&bpmp TEGRA264_CLK_VPLLX_SOR1_MUXED>,
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<&bpmp TEGRA264_CLK_VPLLX_SOR2_MUXED>,
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<&bpmp TEGRA264_CLK_VPLLX_SOR3_MUXED>,
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<&bpmp TEGRA264_CLK_SF0_SOR>,
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<&bpmp TEGRA264_CLK_SF1_SOR>,
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<&bpmp TEGRA264_CLK_SF2_SOR>,
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<&bpmp TEGRA264_CLK_SF3_SOR>,
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<&bpmp TEGRA264_CLK_SF4_SOR>,
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<&bpmp TEGRA264_CLK_SF5_SOR>,
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<&bpmp TEGRA264_CLK_SF6_SOR>,
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<&bpmp TEGRA264_CLK_SF7_SOR>,
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<&bpmp TEGRA264_CLK_DPAUX>,
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<&bpmp TEGRA264_CLK_EMC>;
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clock-names = "nvdisplayhub_clk",
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"nvdisplay_disp_clk",
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"nvdisplay_p0_clk",
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"nvdisplay_p1_clk",
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"nvdisplay_p2_clk",
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"nvdisplay_p3_clk",
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"nvdisplay_p4_clk",
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"nvdisplay_p5_clk",
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"nvdisplay_p6_clk",
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"nvdisplay_p7_clk",
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"fuse_clk",
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"sppll0_clkouta_clk",
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"sppll0_clkoutb_clk",
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"sppll0_clkoutpn_clk",
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"sppll1_clkoutpn_clk",
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"sppll0_div27_clk",
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"sppll1_div27_clk",
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"vpll0_clk",
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"vpll1_clk",
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"vpll2_clk",
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"vpll3_clk",
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"vpll4_clk",
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|
"vpll5_clk",
|
|
"vpll6_clk",
|
|
"vpll7_clk",
|
|
"rg0_clk",
|
|
"rg1_clk",
|
|
"rg2_clk",
|
|
"rg3_clk",
|
|
"rg4_clk",
|
|
"rg5_clk",
|
|
"rg6_clk",
|
|
"rg7_clk",
|
|
"disppll_clk",
|
|
"pre_sor0_clk",
|
|
"pre_sor1_clk",
|
|
"pre_sor2_clk",
|
|
"pre_sor3_clk",
|
|
"dp_link_ref_clk",
|
|
"dp_linkb_ref_clk",
|
|
"dp_linkc_ref_clk",
|
|
"dp_linkd_ref_clk",
|
|
"sor_linka_input_clk",
|
|
"sor_linkb_input_clk",
|
|
"sor_linkc_input_clk",
|
|
"sor_linkd_input_clk",
|
|
"sor_linka_afifo_clk",
|
|
"sor_linkb_afifo_clk",
|
|
"sor_linkc_afifo_clk",
|
|
"sor_linkd_afifo_clk",
|
|
"sor0_clk",
|
|
"sor1_clk",
|
|
"sor2_clk",
|
|
"sor3_clk",
|
|
"sor_pad_input_clk",
|
|
"sor_padb_input_clk",
|
|
"sor_padc_input_clk",
|
|
"sor_padd_input_clk",
|
|
"sor0_pad_clk",
|
|
"sor1_pad_clk",
|
|
"sor2_pad_clk",
|
|
"sor3_pad_clk",
|
|
"sf0_clk",
|
|
"sf1_clk",
|
|
"sf2_clk",
|
|
"sf3_clk",
|
|
"sf4_clk",
|
|
"sf5_clk",
|
|
"sf6_clk",
|
|
"sf7_clk",
|
|
"sor0_ref_pll_clk",
|
|
"sor1_ref_pll_clk",
|
|
"sor2_ref_pll_clk",
|
|
"sor3_ref_pll_clk",
|
|
"sor0_ref_clk",
|
|
"sor1_ref_clk",
|
|
"sor2_ref_clk",
|
|
"sor3_ref_clk",
|
|
"osc_clk",
|
|
"dsc_clk",
|
|
"maud_clk",
|
|
"aza_2xbit_clk",
|
|
"disp_root",
|
|
"vpllx_sor0_muxed_clk",
|
|
"vpllx_sor1_muxed_clk",
|
|
"vpllx_sor2_muxed_clk",
|
|
"vpllx_sor3_muxed_clk",
|
|
"sf0_sor_clk",
|
|
"sf1_sor_clk",
|
|
"sf2_sor_clk",
|
|
"sf3_sor_clk",
|
|
"sf4_sor_clk",
|
|
"sf5_sor_clk",
|
|
"sf6_sor_clk",
|
|
"sf7_sor_clk",
|
|
"dpaux0_clk",
|
|
"emc_clk";
|
|
nvidia,disp-sw-soc-chip-id = <0x2650>;
|
|
resets = <&bpmp TEGRA264_RESET_DPAUX>,
|
|
<&bpmp TEGRA264_RESET_HDACODEC>;
|
|
reset-names = "dpaux0_reset, hdacodec_reset";
|
|
interconnects = <&mc TEGRA264_MEMORY_CLIENT_DISPR &emc>;
|
|
interconnect-names = "read-1";
|
|
status = "disabled";
|
|
iommus = <&smmu3_mmu 0x900>;
|
|
non-coherent;
|
|
};
|