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+ Add the following data validation checks based on
gaps identified when inspecting code for
SHR-9320:
+ FSYNC: Add check to ensure existence of generators
property before parse
+ FSYNC: Add check to ensure generators in default
group adhere to LCM rule
+ CDI: Add check to ensure reg_len / dat_len do
not exceed 2 bytes
+ CDI: Ensure err is set before jumping to err_probe
+ CDI: Jump to err_probe if IOExpander i2c-bus read
fails
+ CDI-TCA: Return error if reg_len or dat_len
out of expected range
+ FuSaCap: Ensure isp/vi-max-channels validated
+ VI: Add check for vi-mapping index found (this was
already caught in existing code, but error message
was non-specific)
+ camera_common: Add check for err that was set but
never read
+ RTCPU: Add debug prints for properties not found
Jira CAMERASW-30537
Change-Id: I9953029f594c0153d6c335913944fb8906adedd9
Signed-off-by: kevixie <kevixie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3280557
Reviewed-by: Vincent Chung <vincentc@nvidia.com>
Reviewed-by: Frank Chen <frankc@nvidia.com>
Reviewed-by: Mohit Ingale <mohiti@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
134 lines
2.9 KiB
C
134 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES.
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* All rights reserved.
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __CDI_TCA9539_PRIV_H__
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#define __CDI_TCA9539_PRIV_H__
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/* i2c payload size is only 12 bit */
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#define MAX_MSG_SIZE (0xFFF - 1)
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struct tca9539_priv {
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struct i2c_adapter *adap;
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int bus;
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u32 addr;
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u32 reg_len;
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u32 dat_len;
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u8 init_val[12];
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u32 power_port;
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u32 fsync_ctrl_port;
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bool enable;
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};
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static int tca9539_raw_wr(
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struct device *dev, struct tca9539_priv *tca9539, unsigned int offset, u8 val)
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{
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int ret = -ENODEV;
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u8 *buf_start = NULL;
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struct i2c_msg *i2cmsg;
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unsigned int num_msgs = 0, total_size, i;
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u8 data[3];
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size_t size = 1;
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dev_dbg(dev, "%s\n", __func__);
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if (tca9539->dat_len != 1)
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return -EINVAL;
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if (tca9539->reg_len != 1)
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return -EINVAL;
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data[0] = (u8)(offset & 0xff);
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data[1] = val;
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size += 1;
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num_msgs = size / MAX_MSG_SIZE;
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num_msgs += (size % MAX_MSG_SIZE) ? 1 : 0;
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i2cmsg = kzalloc((sizeof(struct i2c_msg)*num_msgs), GFP_KERNEL);
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if (!i2cmsg) {
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return -ENOMEM;
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}
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buf_start = data;
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total_size = size;
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dev_dbg(dev, "%s: num_msgs: %d\n", __func__, num_msgs);
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for (i = 0; i < num_msgs; i++) {
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i2cmsg[i].addr = tca9539->addr;
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i2cmsg[i].buf = (__u8 *)buf_start;
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if (i > 0)
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i2cmsg[i].flags = I2C_M_NOSTART;
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else
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i2cmsg[i].flags = 0;
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if (total_size > MAX_MSG_SIZE) {
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i2cmsg[i].len = MAX_MSG_SIZE;
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buf_start += MAX_MSG_SIZE;
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total_size -= MAX_MSG_SIZE;
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} else {
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i2cmsg[i].len = total_size;
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}
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dev_dbg(dev, "%s: addr:%x buf:%p, flags:%u len:%u\n",
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__func__, i2cmsg[i].addr, (void *)i2cmsg[i].buf,
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i2cmsg[i].flags, i2cmsg[i].len);
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}
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ret = i2c_transfer(tca9539->adap, i2cmsg, num_msgs);
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if (ret > 0)
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ret = 0;
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kfree(i2cmsg);
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return ret;
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}
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static int tca9539_raw_rd(
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struct device *dev, struct tca9539_priv *tca9539, unsigned int offset, u8 *val)
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{
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int ret = -ENODEV;
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u8 data[2];
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size_t size = 1;
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struct i2c_msg i2cmsg[2];
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dev_dbg(dev, "%s\n", __func__);
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if (tca9539->dat_len != 1)
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return -EINVAL;
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if (tca9539->reg_len != 1)
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return -EINVAL;
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data[0] = (u8)(offset & 0xff);
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i2cmsg[0].addr = tca9539->addr;
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i2cmsg[0].len = tca9539->reg_len;
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i2cmsg[0].buf = (__u8 *)data;
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i2cmsg[0].flags = I2C_M_NOSTART;
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i2cmsg[1].addr = tca9539->addr;
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i2cmsg[1].flags = I2C_M_RD;
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i2cmsg[1].len = size;
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i2cmsg[1].buf = (__u8 *)val;
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ret = i2c_transfer(tca9539->adap, i2cmsg, 2);
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if (ret > 0)
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ret = 0;
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return ret;
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}
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#endif /* __CDI_TCA9539_PRIV_H__ */
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