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b8e8f99bbd
Linux v5.x kernels are no longer supported and so remove all the legacy UFS related headers for these kernels. Bug 3978622 JIRA LINQPJ14-47 Change-Id: I6e514305d30f93d74bd75fc335db69ced79b3866 Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3349975 GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
37 lines
1.3 KiB
C
37 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2015-2023, The Linux Foundation. All rights reserved. */
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/* SPDX-FileCopyrightText: Copyright (c) 2025, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
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#ifndef UFSHCD_PLTFRM_H_
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#define UFSHCD_PLTFRM_H_
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#include <ufs/ufshcd.h>
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#define UFS_PWM_MODE 1
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#define UFS_HS_MODE 2
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struct ufs_dev_params {
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u32 pwm_rx_gear; /* pwm rx gear to work in */
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u32 pwm_tx_gear; /* pwm tx gear to work in */
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u32 hs_rx_gear; /* hs rx gear to work in */
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u32 hs_tx_gear; /* hs tx gear to work in */
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u32 rx_lanes; /* number of rx lanes */
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u32 tx_lanes; /* number of tx lanes */
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u32 rx_pwr_pwm; /* rx pwm working pwr */
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u32 tx_pwr_pwm; /* tx pwm working pwr */
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u32 rx_pwr_hs; /* rx hs working pwr */
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u32 tx_pwr_hs; /* tx hs working pwr */
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u32 hs_rate; /* rate A/B to work in HS */
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u32 desired_working_mode;
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};
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int ufshcd_get_pwr_dev_param(struct ufs_dev_params *dev_param,
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struct ufs_pa_layer_attr *dev_max,
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struct ufs_pa_layer_attr *agreed_pwr);
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void ufshcd_init_pwr_dev_param(struct ufs_dev_params *dev_param);
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int ufshcd_pltfrm_init(struct platform_device *pdev,
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const struct ufs_hba_variant_ops *vops);
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void ufshcd_pltfrm_shutdown(struct platform_device *pdev);
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#endif /* UFSHCD_PLTFRM_H_ */
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