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git://nv-tegra.nvidia.com/linux-nv-oot.git
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be01df015d
Add support for configurable interrupt timers and event notification queues to SIPL Device Block to mirror the CDAC (QNX) pulse channel interface. The CDI_MGR_IOCTL_INTR_CONFIG IOCTL is added to set the timeout duration at initialization, and existing GPIO interrupt code is refactored. Also removes the GPIO index limitation to the range of [0,31] by returning the complete indices one at a time instead of a bit flag. Jira CAMERASW-11100 Jira CAMERASW-11385 Jira CAMERASW-9366 Bug 3902416 Bug 3792904 Signed-off-by: Vincent Chung <vincentc@nvidia.com> Change-Id: I62b6c0bd8be18922ab1fe5d40485a69274f2a18e Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2893327 Reviewed-by: Semi Malinen <smalinen@nvidia.com> Reviewed-by: Shiva Dubey <sdubey@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
94 lines
2.3 KiB
C
94 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2020-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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#ifndef __UAPI_TEGRA_CDI_MGR_H__
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#define __UAPI_TEGRA_CDI_MGR_H__
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#include <linux/ioctl.h>
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#include <linux/types.h>
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#define CDI_MGR_IOCTL_PWR_DN _IOW('o', 1, __s16)
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#define CDI_MGR_IOCTL_PWR_UP _IOR('o', 2, __s16)
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#define CDI_MGR_IOCTL_SET_PID _IOW('o', 3, struct cdi_mgr_sinfo)
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#define CDI_MGR_IOCTL_SIGNAL _IOW('o', 4, int)
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#define CDI_MGR_IOCTL_DEV_ADD _IOW('o', 5, struct cdi_mgr_new_dev)
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#define CDI_MGR_IOCTL_DEV_DEL _IOW('o', 6, int)
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#define CDI_MGR_IOCTL_PWR_INFO _IOW('o', 7, struct cdi_mgr_pwr_info)
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#define CDI_MGR_IOCTL_PWM_ENABLE _IOW('o', 8, int)
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#define CDI_MGR_IOCTL_PWM_CONFIG _IOW('o', 9, struct cdi_mgr_pwm_info)
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#define CDI_MGR_IOCTL_INTR_CONFIG _IOW('o', 10, struct cdi_mgr_gpio_info)
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#define CDI_MGR_IOCTL_INTR_ENABLE _IO('o', 11)
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#define CDI_MGR_IOCTL_INTR_WAIT _IOR('o', 12, __u32)
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#define CDI_MGR_IOCTL_INTR_WAIT_ABORT _IO('o', 13)
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#define CDI_MGR_IOCTL_GET_EXT_PWR_CTRL _IOR('o', 14, __u8)
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#define CDI_MGR_IOCTL_GET_PWR_INFO _IOW('o', 15, struct cdi_mgr_pwr_ctrl_info)
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#define CDI_MGR_IOCTL_ENABLE_DES_POWER _IO('o', 16)
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#define CDI_MGR_IOCTL_DISABLE_DES_POWER _IO('o', 17)
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#define CDI_MGR_POWER_ALL 5
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#define MAX_CDI_NAME_LENGTH 32
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#define DES_PWR_NVCCP 0U
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#define DES_PWR_GPIO 1U
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#define DES_PWR_NO_PWR 0xFFU
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#define CAM_PWR_NVCCP 0U
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#define CAM_PWR_MAX20087 1U
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#define CAM_PWR_NO_PWR 0xFFU
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struct cdi_mgr_new_dev {
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__u16 addr;
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__u8 reg_bits;
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__u8 val_bits;
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__u8 drv_name[MAX_CDI_NAME_LENGTH];
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};
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struct cdi_mgr_sinfo {
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__s32 pid;
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__s32 sig_no;
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__u64 context;
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};
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struct cdi_mgr_pwr_info {
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__s32 pwr_gpio;
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__s32 pwr_status;
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};
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struct cdi_mgr_pwr_ctrl_info {
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__s8 des_pwr_method;
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__s8 des_pwr_i2c_addr;
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};
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struct cdi_mgr_gpio_info {
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__u32 idx;
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__u32 timeout_ms;
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};
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struct cdi_mgr_gpio_intr {
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__u32 idx;
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__u32 code;
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};
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struct cdi_mgr_pwm_info {
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__u64 duty_ns;
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__u64 period_ns;
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};
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enum {
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CDI_MGR_GPIO_INTR_UNBLOCK = 0,
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CDI_MGR_GPIO_INTR,
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CDI_MGR_GPIO_INTR_TIMEOUT,
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};
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enum {
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CDI_MGR_SIGNAL_RESUME = 0,
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CDI_MGR_SIGNAL_SUSPEND,
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};
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enum {
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CDI_MGR_PWM_DISABLE = 0,
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CDI_MGR_PWM_ENABLE,
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};
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#endif /* __UAPI_TEGRA_CDI_MGR_H__ */
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