mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
synced 2025-12-24 02:01:36 +03:00
c9759f1ef7
Add devices nodes for Multimedia, DLA, PVA and GPU devices. Bug 3724727 Change-Id: Ica4821bb841b14cb85ce18e7c5fd5f3801295c41 Signed-off-by: Brad Griffis <bgriffis@nvidia.com> Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2771894 (cherry picked from commit 8024d27b5ac1771e818681d3387f7375cd93c876) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2757875 Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
370 lines
12 KiB
Devicetree
370 lines
12 KiB
Devicetree
/*
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* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/clock/tegra234-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/memory/tegra234-mc.h>
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#include <dt-bindings/power/tegra234-powergate.h>
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#include <dt-bindings/reset/tegra234-reset.h>
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#define TEGRA234_CLK_NVJPG1 20U
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#define TEGRA234_CLK_GPC0CLK 41U
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#define TEGRA234_CLK_NVDEC 83U
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#define TEGRA234_CLK_NVENC 89U
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#define TEGRA234_CLK_NVJPG 90U
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#define TEGRA234_CLK_TSEC_PKA 154U
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#define TEGRA234_CLK_DLA0_FALCON 174U
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#define TEGRA234_CLK_DLA0_CORE 175U
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#define TEGRA234_CLK_DLA1_FALCON 176U
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#define TEGRA234_CLK_DLA1_CORE 177U
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#define TEGRA234_CLK_NAFLL_PVA0_CORE 211U
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#define TEGRA234_CLK_NAFLL_PVA0_VPS 212U
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#define TEGRA234_CLK_GPC1CLK 236U
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#define TEGRA234_CLK_PVA0_CPU_AXI 295U
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#define TEGRA234_CLK_PVA0_VPS 297U
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#define TEGRA234_CLK_GPUSYS 304U
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#define TEGRA234_CLK_OFA 334U
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#define TEGRA234_MEMORY_CLIENT_NVENCSRD 0x1c
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#define TEGRA234_MEMORY_CLIENT_NVENCSWR 0x2b
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#define TEGRA234_MEMORY_CLIENT_DLA0RDB 0x2c
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#define TEGRA234_MEMORY_CLIENT_DLA0RDB1 0x2d
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#define TEGRA234_MEMORY_CLIENT_DLA0WRB 0x2e
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#define TEGRA234_MEMORY_CLIENT_DLA1RDB 0x2f
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#define TEGRA234_MEMORY_CLIENT_OFAR1 0x3a
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#define TEGRA234_MEMORY_CLIENT_OFAR 0x5d
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#define TEGRA234_MEMORY_CLIENT_OFAW 0x5e
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#define TEGRA234_MEMORY_CLIENT_DLA1RDB1 0x6e
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#define TEGRA234_MEMORY_CLIENT_DLA1WRB 0x6f
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#define TEGRA234_MEMORY_CLIENT_NVDECSRD 0x78
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#define TEGRA234_MEMORY_CLIENT_NVDECSWR 0x79
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#define TEGRA234_MEMORY_CLIENT_NVJPGSRD 0x7e
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#define TEGRA234_MEMORY_CLIENT_NVJPGSWR 0x7f
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#define TEGRA234_MEMORY_CLIENT_DLA0RDA 0xbe
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#define TEGRA234_MEMORY_CLIENT_DLA0FALRDB 0xbf
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#define TEGRA234_MEMORY_CLIENT_DLA0WRA 0xc0
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#define TEGRA234_MEMORY_CLIENT_DLA0FALWRB 0xc1
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#define TEGRA234_MEMORY_CLIENT_DLA1RDA 0xc2
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#define TEGRA234_MEMORY_CLIENT_DLA1FALRDB 0xc3
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#define TEGRA234_MEMORY_CLIENT_DLA1WRA 0xc4
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#define TEGRA234_MEMORY_CLIENT_DLA1FALWRB 0xc5
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#define TEGRA234_MEMORY_CLIENT_PVA0RDA 0xc6
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#define TEGRA234_MEMORY_CLIENT_PVA0RDB 0xc7
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#define TEGRA234_MEMORY_CLIENT_PVA0RDC 0xc8
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#define TEGRA234_MEMORY_CLIENT_PVA0WRA 0xc9
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#define TEGRA234_MEMORY_CLIENT_PVA0WRB 0xca
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#define TEGRA234_MEMORY_CLIENT_PVA0WRC 0xcb
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#define TEGRA234_MEMORY_CLIENT_DLA0RDA1 0xe9
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#define TEGRA234_MEMORY_CLIENT_DLA1RDA1 0xea
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#define TEGRA234_MEMORY_CLIENT_PVA0RDA1 0xeb
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#define TEGRA234_MEMORY_CLIENT_PVA0RDB1 0xec
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#define TEGRA234_MEMORY_CLIENT_NVENCSRD1 0xf0
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#define TEGRA234_MEMORY_CLIENT_NVJPG1SRD 0x123
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#define TEGRA234_MEMORY_CLIENT_NVJPG1SWR 0x124
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#define TEGRA234_RESET_DLA0 6U
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#define TEGRA234_RESET_DLA1 7U
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#define TEGRA234_RESET_OFA 9U
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#define TEGRA234_RESET_NVJPG1 10U
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#define TEGRA234_RESET_GPU 19U
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#define TEGRA234_RESET_NVDEC 44U
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#define TEGRA234_RESET_NVENC 59U
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#define TEGRA234_RESET_NVJPG 61U
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#define TEGRA234_RESET_PVA0_ALL 66U
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#define TEGRA234_POWER_DOMAIN_OFA 1U
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#define TEGRA234_POWER_DOMAIN_NVDEC 23U
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#define TEGRA234_POWER_DOMAIN_NVJPGA 24U
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#define TEGRA234_POWER_DOMAIN_NVENC 25U
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#define TEGRA234_POWER_DOMAIN_VIC 29U
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#define TEGRA234_POWER_DOMAIN_PVA 30U
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#define TEGRA234_POWER_DOMAIN_DLAA 32U
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#define TEGRA234_POWER_DOMAIN_DLAB 33U
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#define TEGRA234_POWER_DOMAIN_GPU 35U
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#define TEGRA234_POWER_DOMAIN_NVJPGB 36U
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#define TEGRA234_SID_NVDLA1 0x23
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#define TEGRA234_SID_NVENC 0x24
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#define TEGRA234_SID_NVJPG1 0x25
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#define TEGRA234_SID_OFA 0x26
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#define TEGRA234_SID_PVA0_VM0 0x12U
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#define TEGRA234_SID_PVA0_VM1 0x13U
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#define TEGRA234_SID_PVA0_VM2 0x14U
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#define TEGRA234_SID_PVA0_VM3 0x15U
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#define TEGRA234_SID_PVA0_VM4 0x16U
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#define TEGRA234_SID_PVA0_VM5 0x17U
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#define TEGRA234_SID_PVA0_VM6 0x18U
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#define TEGRA234_SID_PVA0_VM7 0x19U
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#define TEGRA234_SID_NVDEC 0x29
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#define TEGRA234_SID_NVJPG 0x2a
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#define TEGRA234_SID_NVDLA0 0x2B
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#define TEGRA234_SID_PVA0 0x2C
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/ {
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overlay-name = "Tegra234 Jetson Overlay";
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compatible = "nvidia,tegra234";
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fragment@0 {
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target-path = "/bus@0/host1x@13e00000";
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__overlay__ {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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ranges = <0x14800000 0x14800000 0x02000000>,
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<0x24700000 0x24700000 0x00080000>;
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nvjpg@15380000 {
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compatible = "nvidia,tegra234-nvjpg";
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reg = <0x15380000 0x00040000>;
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clocks = <&bpmp TEGRA234_CLK_NVJPG>;
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clock-names = "nvjpg";
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resets = <&bpmp TEGRA234_RESET_NVJPG>;
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reset-names = "nvjpg";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVJPGA>;
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interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVJPGSRD &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_NVJPGSWR &emc>;
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interconnect-names = "dma-mem", "write";
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iommus = <&smmu_niso1 TEGRA234_SID_NVJPG>;
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dma-coherent;
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nvidia,host1x-class = <0xc0>;
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};
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nvdec@15480000 {
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compatible = "nvidia,tegra234-nvdec";
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reg = <0x15480000 0x00040000>;
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clocks = <&bpmp TEGRA234_CLK_NVDEC>,
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<&bpmp TEGRA234_CLK_FUSE>,
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<&bpmp TEGRA234_CLK_TSEC_PKA>;
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clock-names = "nvdec", "fuse", "tsec_pka";
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resets = <&bpmp TEGRA234_RESET_NVDEC>;
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reset-names = "nvdec";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
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interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>;
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interconnect-names = "dma-mem", "write";
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iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>;
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dma-coherent;
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nvidia,memory-controller = <&mc>;
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};
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nvenc@154c0000 {
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compatible = "nvidia,tegra234-nvenc";
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reg = <0x154c0000 0x00040000>;
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clocks = <&bpmp TEGRA234_CLK_NVENC>;
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clock-names = "nvenc";
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resets = <&bpmp TEGRA234_RESET_NVENC>;
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reset-names = "nvenc";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVENC>;
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interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVENCSRD &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_NVENCSWR &emc>;
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interconnect-names = "dma-mem", "write";
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iommus = <&smmu_niso0 TEGRA234_SID_NVENC>;
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dma-coherent;
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};
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nvjpg@15540000 {
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compatible = "nvidia,tegra234-nvjpg";
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reg = <0x15540000 0x00040000>;
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clocks = <&bpmp TEGRA234_CLK_NVJPG1>;
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clock-names = "nvjpg";
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resets = <&bpmp TEGRA234_RESET_NVJPG1>;
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reset-names = "nvjpg";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVJPGB>;
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interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVJPG1SRD &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_NVJPG1SWR &emc>;
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interconnect-names = "dma-mem", "write";
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iommus = <&smmu_niso0 TEGRA234_SID_NVJPG1>;
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dma-coherent;
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nvidia,host1x-class = <0x07>;
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};
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nvdla0: nvdla0@15880000 {
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compatible = "nvidia,tegra234-nvdla";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DLAA>;
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reg = <0x15880000 0x00040000>;
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interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&bpmp TEGRA234_RESET_DLA0>;
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clocks = <&bpmp TEGRA234_CLK_DLA0_CORE>,
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<&bpmp TEGRA234_CLK_DLA0_FALCON>;
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clock-names = "nvdla0", "nvdla0_flcn";
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interconnects = <&mc TEGRA234_MEMORY_CLIENT_DLA0RDA &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_DLA0FALRDB &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_DLA0WRA &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_DLA0FALWRB &emc>;
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interconnect-names = "dma-mem", "read-1", "write", "write-1";
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iommus = <&smmu_niso1 TEGRA234_SID_NVDLA0>;
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dma-coherent;
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status = "okay";
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};
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nvdla1: nvdla1@158c0000 {
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compatible = "nvidia,tegra234-nvdla";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DLAB>;
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reg = <0x158c0000 0x00040000>;
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interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&bpmp TEGRA234_RESET_DLA1>;
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clocks = <&bpmp TEGRA234_CLK_DLA1_CORE>,
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<&bpmp TEGRA234_CLK_DLA1_FALCON>;
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clock-names = "nvdla1", "nvdla1_flcn";
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interconnects = <&mc TEGRA234_MEMORY_CLIENT_DLA1RDA &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_DLA1FALRDB &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_DLA1WRA &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_DLA1FALWRB &emc>;
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interconnect-names = "dma-mem", "read-1", "write", "write-1";
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iommus = <&smmu_niso0 TEGRA234_SID_NVDLA1>;
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dma-coherent;
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status = "okay";
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};
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ofa@15a50000 {
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compatible = "nvidia,tegra234-ofa";
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reg = <0x15a50000 0x00040000>;
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clocks = <&bpmp TEGRA234_CLK_OFA>;
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clock-names = "ofa";
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resets = <&bpmp TEGRA234_RESET_OFA>;
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reset-names = "ofa";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_OFA>;
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interconnects = <&mc TEGRA234_MEMORY_CLIENT_OFAR &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_OFAW &emc>;
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interconnect-names = "dma-mem", "write";
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iommus = <&smmu_niso0 TEGRA234_SID_OFA>;
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dma-coherent;
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};
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pva0: pva0@16000000 {
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compatible = "nvidia,tegra234-pva";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PVA>;
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reg = <0x16000000 0x800000>,
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<0x24700000 0x080000>;
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interrupts = <0 234 0x04>,
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<0 432 0x04>,
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<0 433 0x04>,
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<0 434 0x04>,
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<0 435 0x04>,
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<0 436 0x04>,
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<0 437 0x04>,
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<0 438 0x04>,
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<0 439 0x04>;
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resets = <&bpmp TEGRA234_RESET_PVA0_ALL>;
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clocks = <&bpmp TEGRA234_CLK_PVA0_CPU_AXI>,
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<&bpmp TEGRA234_CLK_NAFLL_PVA0_VPS>,
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<&bpmp TEGRA234_CLK_PVA0_VPS>;
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clock-names = "axi", "vps0", "vps1";
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iommus = <&smmu_niso1 TEGRA234_SID_PVA0>;
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dma-coherent;
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status = "okay";
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pva0_ctx0n1: pva0_niso1_ctx0 {
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compatible = "nvidia,pva-tegra186-iommu-context";
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iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM0>;
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dma-coherent;
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status = "okay";
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};
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pva0_ctx1n1: pva0_niso1_ctx1 {
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compatible = "nvidia,pva-tegra186-iommu-context";
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iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM1>;
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dma-coherent;
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status = "okay";
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};
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pva0_ctx2n1: pva0_niso1_ctx2 {
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compatible = "nvidia,pva-tegra186-iommu-context";
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iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM2>;
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dma-coherent;
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status = "okay";
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};
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pva0_ctx3n1: pva0_niso1_ctx3 {
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compatible = "nvidia,pva-tegra186-iommu-context";
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iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM3>;
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dma-coherent;
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status = "okay";
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};
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pva0_ctx4n1: pva0_niso1_ctx4 {
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compatible = "nvidia,pva-tegra186-iommu-context";
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iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM4>;
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dma-coherent;
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status = "okay";
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};
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pva0_ctx5n1: pva0_niso1_ctx5 {
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compatible = "nvidia,pva-tegra186-iommu-context";
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iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM5>;
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dma-coherent;
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status = "okay";
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};
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pva0_ctx6n1: pva0_niso1_ctx6 {
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compatible = "nvidia,pva-tegra186-iommu-context";
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iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM6>;
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dma-coherent;
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status = "okay";
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};
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pva0_ctx7n1: pva0_niso1_ctx7 {
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compatible = "nvidia,pva-tegra186-iommu-context";
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iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM7>;
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dma-coherent;
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status = "okay";
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};
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};
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};
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};
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fragment@1 {
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target-path = "/bus@0";
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__overlay__ {
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#address-cells = <1>;
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#size-cells = <1>;
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gpu@17000000 {
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compatible = "nvidia,ga10b";
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reg = <0x17000000 0x01000000>,
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<0x18000000 0x01000000>,
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<0x03b41000 0x00001000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "stall0", "stall1", "stall2", "nonstall";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_GPU>;
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clocks = <&bpmp TEGRA234_CLK_GPUSYS>,
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<&bpmp TEGRA234_CLK_GPC0CLK>,
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<&bpmp TEGRA234_CLK_GPC1CLK>;
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clock-names = "sysclk", "gpc0clk", "gpc1clk";
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resets = <&bpmp TEGRA234_RESET_GPU>;
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dma-coherent;
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nvidia,bpmp = <&bpmp>;
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status = "okay";
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};
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};
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};
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};
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