mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
synced 2025-12-24 10:11:26 +03:00
0d01039657
Tegra234 tachometer supports FAN speed in rpm. This change is added to enable tachometer module. Bug 3771589 Change-Id: Iec98e32c50bb43f47eb64af41a8d25c6175f96f1 Signed-off-by: Sandipan Patra <spatra@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2775691 Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
293 lines
8.3 KiB
Devicetree
293 lines
8.3 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0
|
|
// Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
|
|
|
|
|
#include <dt-bindings/clock/tegra234-clock.h>
|
|
#include <dt-bindings/clock/tegra234-clock-oot.h>
|
|
#include <dt-bindings/reset/tegra234-reset.h>
|
|
#include <dt-bindings/reset/tegra234-reset-oot.h>
|
|
#include <dt-bindings/memory/tegra234-mc.h>
|
|
#include <dt-bindings/memory/tegra234-mc-oot.h>
|
|
#include <dt-bindings/memory/tegra234-smmu-streamid.h>
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
|
|
/ {
|
|
overlay-name = "Add nvidia,p3737-0000+p3701-0000 Overlay Support";
|
|
compatible = "nvidia,tegra234";
|
|
|
|
fragment-t234@0 {
|
|
target-path = "/bus@0";
|
|
__overlay__ {
|
|
watchdog@2190000 {
|
|
compatible = "nvidia,tegra-wdt-t234";
|
|
reg = <0x02190000 0x10000>, /* WDT0 */
|
|
<0x02090000 0x10000>, /* TMR0 */
|
|
<0x02080000 0x10000>; /* TKE */
|
|
interrupts = <7 0x4 8 0x4>; /* TKE shared int */
|
|
nvidia,watchdog-index = <0>;
|
|
nvidia,timer-index = <7>;
|
|
nvidia,enable-on-init;
|
|
nvidia,extend-watchdog-suspend;
|
|
timeout-sec = <120>;
|
|
nvidia,disable-debug-reset;
|
|
status = "okay";
|
|
};
|
|
|
|
tegra_ufs: ufshci@2500000 {
|
|
compatible = "tegra234,ufs_variant";
|
|
reg = <0x02500000 0x4000>,
|
|
<0x02510000 0x1000>,
|
|
<0x02518000 0x1000>,
|
|
<0x02520000 0x1000>,
|
|
<0x02470000 0x4000>,
|
|
<0x02480000 0x4000>;
|
|
interrupts = < 0 44 0x04 >;
|
|
interconnects = <&mc TEGRA234_MEMORY_CLIENT_UFSHCR>,
|
|
<&mc TEGRA234_MEMORY_CLIENT_UFSHCW>;
|
|
interconnect-names = "dma-mem", "dma-mem";
|
|
iommus = <&smmu_niso0 TEGRA234_SID_UFSHC>;
|
|
dma-coherent;
|
|
clocks = <&bpmp TEGRA234_CLK_PLLREFE_VCOOUT>,
|
|
<&bpmp TEGRA234_CLK_MPHY_CORE_PLL_FIXED>,
|
|
<&bpmp TEGRA234_CLK_MPHY_L0_TX_SYMB>,
|
|
<&bpmp TEGRA234_CLK_MPHY_TX_1MHZ_REF>,
|
|
<&bpmp TEGRA234_CLK_MPHY_L0_RX_ANA>,
|
|
<&bpmp TEGRA234_CLK_MPHY_L0_RX_SYMB>,
|
|
<&bpmp TEGRA234_CLK_MPHY_L0_TX_LS_3XBIT>,
|
|
<&bpmp TEGRA234_CLK_MPHY_L0_RX_LS_BIT>,
|
|
<&bpmp TEGRA234_CLK_MPHY_L1_RX_ANA>,
|
|
<&bpmp TEGRA234_CLK_UFSHC>,
|
|
<&bpmp TEGRA234_CLK_UFSDEV_REF>,
|
|
<&bpmp TEGRA234_CLK_PLLP_OUT0>,
|
|
<&bpmp TEGRA234_CLK_CLK_M>,
|
|
<&bpmp TEGRA234_CLK_MPHY_FORCE_LS_MODE>,
|
|
<&bpmp TEGRA234_CLK_UPHY_PLL3>,
|
|
<&bpmp TEGRA234_CLK_MPHY_L0_TX_LS_3XBIT_DIV>,
|
|
<&bpmp TEGRA234_CLK_MPHY_L0_TX_LS_SYMB_DIV>,
|
|
<&bpmp TEGRA234_CLK_MPHY_L0_RX_LS_BIT_DIV>,
|
|
<&bpmp TEGRA234_CLK_MPHY_L0_RX_LS_SYMB_DIV>,
|
|
<&bpmp TEGRA234_CLK_MPHY_L0_TX_2X_SYMB>,
|
|
<&bpmp TEGRA234_CLK_MPHY_L0_TX_HS_SYMB_DIV>,
|
|
<&bpmp TEGRA234_CLK_MPHY_L0_RX_HS_SYMB_DIV>,
|
|
<&bpmp TEGRA234_CLK_MPHY_L0_TX_MUX_SYMB_DIV>,
|
|
<&bpmp TEGRA234_CLK_MPHY_L0_RX_MUX_SYMB_DIV>,
|
|
<&bpmp TEGRA234_CLK_OSC>;
|
|
clock-names = "pllrefe_vcoout", "mphy_core_pll_fixed",
|
|
"mphy_l0_tx_symb", "mphy_tx_1mhz_ref",
|
|
"mphy_l0_rx_ana", "mphy_l0_rx_symb",
|
|
"mphy_l0_tx_ls_3xbit", "mphy_l0_rx_ls_bit",
|
|
"mphy_l1_rx_ana", "ufshc", "ufsdev_ref",
|
|
"pll_p", "clk_m", "mphy_force_ls_mode",
|
|
"uphy_pll3", "mphy_l0_tx_ls_3xbit_div",
|
|
"mphy_l0_tx_ls_symb_div",
|
|
"mphy_l0_rx_ls_bit_div",
|
|
"mphy_l0_rx_ls_symb_div",
|
|
"mphy_l0_tx_2x_symb",
|
|
"mphy_l0_tx_hs_symb_div",
|
|
"mphy_l0_rx_hs_symb_div",
|
|
"mphy_l0_tx_mux_symb_div",
|
|
"mphy_l0_rx_mux_symb_div", "osc";
|
|
resets = <&bpmp TEGRA234_RESET_MPHY_L0_RX>,
|
|
<&bpmp TEGRA234_RESET_MPHY_L0_TX>,
|
|
<&bpmp TEGRA234_RESET_MPHY_L1_RX>,
|
|
<&bpmp TEGRA234_RESET_MPHY_L1_TX>,
|
|
<&bpmp TEGRA234_RESET_MPHY_CLK_CTL>,
|
|
<&bpmp TEGRA234_RESET_UFSHC>,
|
|
<&bpmp TEGRA234_RESET_UFSHC_AXI_M>,
|
|
<&bpmp TEGRA234_RESET_UFSHC_LP_SEQ>;
|
|
reset-names = "mphy-l0-rx-rst", "mphy-l0-tx-rst",
|
|
"mphy-l1-rx-rst", "mphy-l1-tx-rst",
|
|
"mphy-clk-ctl-rst", "ufs-rst",
|
|
"ufs-axi-m-rst", "ufshc-lp-rst";
|
|
nvidia,enable-x2-config;
|
|
nvidia,mask-fast-auto-mode;
|
|
nvidia,enable-hs-mode;
|
|
nvidia,max-hs-gear = <4>;
|
|
nvidia,max-pwm-gear = <0>;
|
|
vcc-max-microamp = <0>;
|
|
vccq-max-microamp = <0>;
|
|
vccq2-max-microamp = <0>;
|
|
nvidia,configure-uphy-pll3;
|
|
status = "disabled";
|
|
|
|
ufs_variant {
|
|
compatible = "tegra234,ufs_variant";
|
|
};
|
|
};
|
|
|
|
gpcdma: gpcdma@2600000 {
|
|
compatible = "nvidia,tegra234-gpcdma";
|
|
reg = <0x2600000 0x210000>;
|
|
resets = <&bpmp TEGRA234_RESET_GPCDMA>;
|
|
reset-names = "gpcdma";
|
|
interrupts = <0 75 0x04
|
|
0 76 0x04
|
|
0 77 0x04
|
|
0 78 0x04
|
|
0 79 0x04
|
|
0 80 0x04
|
|
0 81 0x04
|
|
0 82 0x04
|
|
0 83 0x04
|
|
0 84 0x04
|
|
0 85 0x04
|
|
0 86 0x04
|
|
0 87 0x04
|
|
0 88 0x04
|
|
0 89 0x04
|
|
0 90 0x04
|
|
0 91 0x04
|
|
0 92 0x04
|
|
0 93 0x04
|
|
0 94 0x04
|
|
0 95 0x04
|
|
0 96 0x04
|
|
0 97 0x04
|
|
0 98 0x04
|
|
0 99 0x04
|
|
0 100 0x04
|
|
0 101 0x04
|
|
0 102 0x04
|
|
0 103 0x04
|
|
0 104 0x04
|
|
0 105 0x04
|
|
0 106 0x04
|
|
0 107 0x04>;
|
|
#dma-cells = <1>;
|
|
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
|
|
dma-coherent;
|
|
nvidia,start-dma-channel-index = <1>;
|
|
dma-channels = <31>;
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
serial@3110000 {
|
|
compatible = "nvidia,tegra194-hsuart";
|
|
reg = <0x03110000 0x10000>;
|
|
reg-shift = <2>;
|
|
interrupts = <0 113 0x04>;
|
|
clocks = <&bpmp TEGRA234_CLK_UARTB>,
|
|
<&bpmp TEGRA234_CLK_PLLP_OUT0>;
|
|
clock-names = "serial", "parent";
|
|
resets = <&bpmp TEGRA234_RESET_UARTB>;
|
|
reset-names = "serial";
|
|
status = "okay";
|
|
};
|
|
|
|
hda@3510000 {
|
|
iommus = <&smmu_niso0 TEGRA234_SID_HDA>;
|
|
status = "okay";
|
|
};
|
|
|
|
rtc@c2a0000 {
|
|
status = "okay";
|
|
};
|
|
|
|
tachometer@39c0000 {
|
|
compatible = "nvidia,pwm-tegra234-tachometer";
|
|
reg = <0x039c0000 0x10>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&bpmp TEGRA234_CLK_TACH0>;
|
|
clock-names = "tach";
|
|
resets = <&bpmp TEGRA234_RESET_TACH0>;
|
|
reset-names = "tach";
|
|
pulse-per-rev = <2>;
|
|
capture-window-length = <2>;
|
|
disable-clk-gate;
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|
|
|
|
fragment-t234@1 {
|
|
target-path = "/bus@0/host1x@13e00000";
|
|
__overlay__ {
|
|
se@15810000 {
|
|
compatible = "nvidia,tegra234-se1-nvhost";
|
|
reg = <0x15810000 0x10000>;
|
|
supported-algos = "drbg";
|
|
nvidia,io-coherent;
|
|
opcode_addr = <0x1004>;
|
|
clocks = <&bpmp TEGRA234_CLK_SE>;
|
|
clock-names = "se";
|
|
|
|
iommus = <&smmu_niso1 TEGRA234_SID_SES_SE0>;
|
|
dma-coherent;
|
|
interconnects = <&mc TEGRA234_MEMORY_CLIENT_SESRD &emc>,
|
|
<&mc TEGRA234_MEMORY_CLIENT_SESWR &emc>;
|
|
interconnect-names = "read", "write";
|
|
status = "okay";
|
|
};
|
|
|
|
se@15820000 {
|
|
compatible = "nvidia,tegra234-se2-nvhost";
|
|
reg = <0x15820000 0x10000>;
|
|
supported-algos = "aes", "cmac", "xts", "aead";
|
|
nvidia,io-coherent;
|
|
opcode_addr = <0x2004>;
|
|
clocks = <&bpmp TEGRA234_CLK_SE>;
|
|
clock-names = "se";
|
|
|
|
iommus = <&smmu_niso1 TEGRA234_SID_SES_SE1>;
|
|
dma-coherent;
|
|
interconnects = <&mc TEGRA234_MEMORY_CLIENT_SESRD &emc>,
|
|
<&mc TEGRA234_MEMORY_CLIENT_SESWR &emc>;
|
|
interconnect-names = "read", "write";
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
se@15840000 {
|
|
compatible = "nvidia,tegra234-se2-nvhost";
|
|
reg = <0x15840000 0x10000>;
|
|
supported-algos = "sha", "sha3", "hmac";
|
|
nvidia,io-coherent;
|
|
opcode_addr = <0x4004>;
|
|
clocks = <&bpmp TEGRA234_CLK_SE>;
|
|
clock-names = "se";
|
|
|
|
iommus = <&smmu_niso1 TEGRA234_SID_SES_SE2>;
|
|
dma-coherent;
|
|
interconnects = <&mc TEGRA234_MEMORY_CLIENT_SESRD &emc>,
|
|
<&mc TEGRA234_MEMORY_CLIENT_SESWR &emc>;
|
|
interconnect-names = "read", "write";
|
|
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|
|
|
|
fragment-t234@2 {
|
|
target-path = "/";
|
|
__overlay__ {
|
|
aliases {
|
|
serial1 = "/bus@0/serial@3110000";
|
|
};
|
|
};
|
|
};
|
|
|
|
fragment-t234@3 {
|
|
target-path = "/";
|
|
__overlay__ {
|
|
tegra_mce@e100000 {
|
|
compatible = "nvidia,t23x-mce";
|
|
reg = <0x0 0x0E100000 0x0 0x00010000>, /* ARI BASE Core 0*/
|
|
<0x0 0x0E110000 0x0 0x00010000>,
|
|
<0x0 0x0E120000 0x0 0x00010000>,
|
|
<0x0 0x0E130000 0x0 0x00010000>,
|
|
<0x0 0x0E140000 0x0 0x00010000>,
|
|
<0x0 0x0E150000 0x0 0x00010000>,
|
|
<0x0 0x0E160000 0x0 0x00010000>,
|
|
<0x0 0x0E170000 0x0 0x00010000>,
|
|
<0x0 0x0E180000 0x0 0x00010000>,
|
|
<0x0 0x0E190000 0x0 0x00010000>,
|
|
<0x0 0x0E1A0000 0x0 0x00010000>,
|
|
<0x0 0x0E1B0000 0x0 0x00010000>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|
|
};
|