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681288f1be
Because of the way in which Makefile is defined for the drivers, each driver file is getting compliled as separate *.ko module. This results in loading of all the *.ko modules for maintaining the functionality. Current patch re-organises makefile and thus terga-alt structure, - utils/ : will provide all the helper functions, - machine_drivers/ : lists all the machine specific drivers we have, - tegra-alt/*.c : ahub module drivers, each would have a separate driver module, - include/ : all the local header files needed for driver modules Bug 200346429 Change-Id: Ic659879a0d6e8ef48b0d79b81059fba4c069591e Signed-off-by: Sameer Pujar <spujar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1559745 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
91 lines
3.2 KiB
C
91 lines
3.2 KiB
C
/*
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* tegra210_iqc_alt.h - Definitions for Tegra210 IQC driver
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*
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* Copyright (c) 2014-2017 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __TEGRA210_IQC_ALT_H__
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#define __TEGRA210_IQC_ALT_H__
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#define TEGRA210_IQC_AXBAR_TX_STRIDE 0x04
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/* Register offsets from TEGRA210_IQC*_BASE */
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/*
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* IQC_AXBAR_TX registers are with respect to AXBAR.
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* The data is coming from IQC for record.
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*/
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#define TEGRA210_IQC_AXBAR_TX_STATUS 0x0c
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#define TEGRA210_IQC_AXBAR_TX_INT_STATUS 0x10
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#define TEGRA210_IQC_AXBAR_TX_INT_MASK 0x14
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#define TEGRA210_IQC_AXBAR_TX_INT_SET 0x18
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#define TEGRA210_IQC_AXBAR_TX_INT_CLEAR 0x1c
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#define TEGRA210_IQC_AXBAR_TX_CIF_CTRL 0x20
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#define TEGRA210_IQC_ENABLE 0x80
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#define TEGRA210_IQC_SOFT_RESET 0x84
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#define TEGRA210_IQC_CG 0x88
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#define TEGRA210_IQC_STATUS 0x8c
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#define TEGRA210_IQC_INT_STATUS 0x90
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#define TEGRA210_IQC_CTRL 0xa0
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#define TEGRA210_IQC_TIME_STAMP_STATUS_0 0xa4
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#define TEGRA210_IQC_TIME_STAMP_STATUS_1 0xa8
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#define TEGRA210_IQC_WS_EDGE_STATUS 0xac
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#define TEGRA210_IQC_CYA 0xb0
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/* Fields in TEGRA210_IQC_ENABLE */
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#define TEGRA210_IQC_EN_SHIFT 0
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#define TEGRA210_IQC_EN_MASK (1 << TEGRA210_IQC_EN_SHIFT)
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#define TEGRA210_IQC_EN (1 << TEGRA210_IQC_EN_SHIFT)
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/* Fields in TEGRA210_IQC_CTRL */
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#define TEGRA210_IQC_CTRL_EDGE_CTRL_SHIFT 4
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#define TEGRA210_IQC_CTRL_EDGE_CTRL_MASK (1 << TEGRA210_IQC_CTRL_EDGE_CTRL_SHIFT)
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#define TEGRA210_IQC_CTRL_EDGE_CTRL_NEG_EDGE (1 << TEGRA210_IQC_CTRL_EDGE_CTRL_SHIFT)
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#define TEGRA210_IQC_TIMESTAMP_SHIFT 5
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#define TEGRA210_IQC_TIMESTAMP_MASK (1 << TEGRA210_IQC_TIMESTAMP_SHIFT)
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#define TEGRA210_IQC_TIMESTAMP_EN (1 << TEGRA210_IQC_TIMESTAMP_SHIFT)
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#define TEGRA210_IQC_WORD_SIZE_SHIFT 8
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#define TEGRA210_IQC_WORD_SIZE_MASK (0xf << TEGRA210_IQC_WORD_SIZE_SHIFT)
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#define TEGRA210_IQC_WS_POLARITY_SHIFT 12
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#define TEGRA210_IQC_WS_POLARITY_MASK (1 << TEGRA210_IQC_WS_POLARITY_SHIFT)
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#define TEGRA210_IQC_WS_POLARITY_HIGH (1 << TEGRA210_IQC_WS_POLARITY_SHIFT)
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#define TEGRA210_IQC_BIT_ORDER_SHIFT 16
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#define TEGRA210_IQC_BIT_ORDER_MASK (1 << TEGRA210_IQC_BIT_ORDER_SHIFT)
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#define TEGRA210_IQC_LSB_FIRST (1 << TEGRA210_IQC_BIT_ORDER_SHIFT)
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#define TEGRA210_IQC_DATA_OFFSET_SHIFT 0
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#define TEGRA210_IQC_DATA_OFFSET_MASK (7 << TEGRA210_IQC_DATA_OFFSET_SHIFT)
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struct tegra210_iqc_soc_data {
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void (*set_audio_cif)(struct regmap *map,
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unsigned int reg,
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struct tegra210_xbar_cif_conf *conf);
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};
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struct tegra210_iqc {
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struct clk *clk_iqc;
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struct regmap *regmap;
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unsigned int timestamp_enable;
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unsigned int data_offset;
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const struct tegra210_iqc_soc_data *soc_data;
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};
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#endif
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