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681288f1be
Because of the way in which Makefile is defined for the drivers, each driver file is getting compliled as separate *.ko module. This results in loading of all the *.ko modules for maintaining the functionality. Current patch re-organises makefile and thus terga-alt structure, - utils/ : will provide all the helper functions, - machine_drivers/ : lists all the machine specific drivers we have, - tegra-alt/*.c : ahub module drivers, each would have a separate driver module, - include/ : all the local header files needed for driver modules Bug 200346429 Change-Id: Ic659879a0d6e8ef48b0d79b81059fba4c069591e Signed-off-by: Sameer Pujar <spujar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1559745 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
54 lines
2.1 KiB
C
54 lines
2.1 KiB
C
/*
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* tegra210_peq_alt.h - Definitions for Tegra210 PEQ driver
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*
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* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __TEGRA210_PEQ_ALT_H__
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#define __TEGRA210_PEQ_ALT_H__
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/* Register offsets from TEGRA210_PEQ*_BASE */
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#define TEGRA210_PEQ_SOFT_RESET 0x0
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#define TEGRA210_PEQ_CG 0x4
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#define TEGRA210_PEQ_STATUS 0x8
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#define TEGRA210_PEQ_CONFIG 0xc
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#define TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_CTRL 0x10
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#define TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_DATA 0x14
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#define TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_CTRL 0x18
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#define TEGRA210_PEQ_AHUBRAMCTL_CONFIG_RAM_SHIFT_DATA 0x1c
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/* Fields in TEGRA210_PEQ_CONFIG */
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#define TEGRA210_PEQ_CONFIG_BIQUAD_STAGES_SHIFT 2
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#define TEGRA210_PEQ_CONfIG_BIQUAD_STAGES_MASK (0xf << TEGRA210_PEQ_CONFIG_BIQUAD_STAGES_SHIFT)
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#define TEGRA210_PEQ_CONFIG_BIAS_SHIFT 1
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#define TEGRA210_PEQ_CONFIG_BIAS_MASK (0x1 << TEGRA210_PEQ_CONFIG_BIAS_SHIFT)
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#define TEGRA210_PEQ_CONFIG_UNBIAS (1 << TEGRA210_PEQ_CONFIG_BIAS_SHIFT)
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#define TEGRA210_PEQ_CONFIG_MODE_SHIFT 0
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#define TEGRA210_PEQ_CONFIG_MODE_MASK (0x1 << TEGRA210_PEQ_CONFIG_MODE_SHIFT)
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#define TEGRA210_PEQ_CONFIG_MODE_ACTIVE (1 << TEGRA210_PEQ_CONFIG_MODE_SHIFT)
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/* PEQ register definition ends here */
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#define TEGRA210_PEQ_MAX_BIQUAD_STAGES 12
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#define TEGRA210_PEQ_MAX_CHANNELS 8
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#define TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH \
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(2 + TEGRA210_PEQ_MAX_BIQUAD_STAGES * 5)
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#define TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH \
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(2 + TEGRA210_PEQ_MAX_BIQUAD_STAGES)
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#endif
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