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ce50d17412
The function tegra_alt_asoc_utils_set_parent() is only used by the Orca Viper machine driver. Update the Orca Viper machine driver to use the tegra_alt_asoc_utils_set_extern_parent() instead which also sets the extern parent clock and remove the redundant tegra_alt_asoc_utils_set_parent() function. Please note that the Orca Viper platform is no longer supported and in future will be removed. Bug 1665446 Change-Id: I51ac355e92a1c3dbb65f94bff081edd1837f7bc6 Signed-off-by: Jonathan Hunter <jonathanh@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2016369 Reviewed-by: Mohan Kumar D <mkumard@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
88 lines
2.5 KiB
C
88 lines
2.5 KiB
C
/*
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* tegra_alt_asoc_utils.h - Definitions for MCLK and DAP Utility driver
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*
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* Author: Stephen Warren <swarren@nvidia.com>
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* Copyright (c) 2011-2019 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#ifndef __TEGRA_ASOC_UTILS_ALT_H_
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#define __TEGRA_ASOC_UTILS_ALT_H_
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struct clk;
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struct device;
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enum tegra_asoc_utils_soc {
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TEGRA_ASOC_UTILS_SOC_TEGRA210,
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TEGRA_ASOC_UTILS_SOC_TEGRA186,
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TEGRA_ASOC_UTILS_SOC_TEGRA194,
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};
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/* Maintain same order in DT entry */
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enum tegra_asoc_utils_clkrate {
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PLLA_x11025_RATE,
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AUD_MCLK_x11025_RATE,
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PLLA_OUT0_x11025_RATE,
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AHUB_x11025_RATE,
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PLLA_x8000_RATE,
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AUD_MCLK_x8000_RATE,
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PLLA_OUT0_x8000_RATE,
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AHUB_x8000_RATE,
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MAX_NUM_RATES,
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};
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struct tegra_asoc_audio_clock_info {
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struct device *dev;
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struct snd_soc_card *card;
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enum tegra_asoc_utils_soc soc;
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struct clk *clk_pll_a;
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struct clk *clk_pll_a_out0;
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struct clk *clk_cdev1;
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struct clk *clk_ahub;
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struct reset_control *clk_cdev1_rst;
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struct clk *clk_m;
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struct clk *clk_pll_p_out1;
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int set_mclk;
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int lock_count;
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int set_baseclock;
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int set_clk_out_rate;
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int num_clk;
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unsigned int clk_out_rate;
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unsigned int mclk_scale;
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u32 clk_rates[MAX_NUM_RATES];
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};
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int tegra_alt_asoc_utils_set_rate(struct tegra_asoc_audio_clock_info *data,
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int srate,
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int mclk,
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int clk_out_rate);
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void tegra_alt_asoc_utils_lock_clk_rate(
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struct tegra_asoc_audio_clock_info *data,
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int lock);
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int tegra_alt_asoc_utils_init(struct tegra_asoc_audio_clock_info *data,
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struct device *dev, struct snd_soc_card *card);
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int tegra_alt_asoc_utils_set_extern_parent(
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struct tegra_asoc_audio_clock_info *data, const char *parent);
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int tegra_alt_asoc_utils_clk_enable(struct tegra_asoc_audio_clock_info *data);
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int tegra_alt_asoc_utils_clk_disable(struct tegra_asoc_audio_clock_info *data);
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int tegra_alt_asoc_utils_register_ctls(struct tegra_asoc_audio_clock_info *data);
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int tegra_alt_asoc_utils_tristate_dap(int id, bool tristate);
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#endif
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