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37dfa4b276
Define tsec_t186_config/tsecb_t186_config and tsec_t186_ops for TSEC Define .load_regs = tsec_load_streamid_regs() for TSEC streamid support Bug 1704301 Change-Id: Ibf3219973627802ee4301c5a23e766d9953dbc3b Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1029501 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
55 lines
1.6 KiB
C
55 lines
1.6 KiB
C
/*
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* Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "drm.h"
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#include "tsec_t186.h"
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#include <linux/iommu.h>
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static int tsec_load_streamid_regs(struct tegra_drm_client *client)
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{
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struct tsec *tsec = to_tsec(client);
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int streamid = -EINVAL;
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streamid = iommu_get_hwid(tsec->dev->archdata.iommu, tsec->dev, 0);
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if (streamid >= 0) {
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tsec_writel(tsec, streamid, TSEC_THI_STREAMID0);
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tsec_writel(tsec, streamid, TSEC_THI_STREAMID1);
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}
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return 0;
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}
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static const struct tegra_drm_client_ops tsec_t186_ops = {
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.open_channel = tsec_open_channel,
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.close_channel = tsec_close_channel,
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.submit = tegra_drm_submit,
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.load_regs = tsec_load_streamid_regs,
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};
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const struct tsec_config tsec_t186_config = {
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.ucode_name = "tegra18x/nvhost_tsec.fw",
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.drm_client_ops = &tsec_t186_ops,
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.class_id = HOST1X_CLASS_TSEC,
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};
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const struct tsec_config tsecb_t186_config = {
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.ucode_name = "tegra18x/nvhost_tsec.fw",
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.drm_client_ops = &tsec_t186_ops,
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.class_id = HOST1X_CLASS_TSECB,
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};
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