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git://nv-tegra.nvidia.com/linux-nv-oot.git
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585f64d7df
Update syncpt name and process info in debug log. Bug 5170956 Change-Id: Ie7db05a60b95febcdc645fe406297e09ad97976f Signed-off-by: Mainak Sen <msen@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3330491 Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
151 lines
3.5 KiB
C
151 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Tegra host1x Syncpoints
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*
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* Copyright (c) 2010-2023, NVIDIA Corporation.
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*/
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#include <linux/io.h>
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#include <soc/tegra/fuse-helper.h>
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#include "../dev.h"
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#include "../syncpt.h"
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/*
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* Write the current syncpoint value back to hw.
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*/
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static void syncpt_restore(struct host1x_syncpt *sp)
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{
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u32 min = host1x_syncpt_read_min(sp);
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struct host1x *host = sp->host;
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host1x_sync_writel(host, min, HOST1X_SYNC_SYNCPT(sp->id));
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}
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/*
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* Write the current waitbase value back to hw.
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*/
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static void syncpt_restore_wait_base(struct host1x_syncpt *sp)
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{
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#if HOST1X_HW < 7
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struct host1x *host = sp->host;
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host1x_sync_writel(host, sp->base_val,
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HOST1X_SYNC_SYNCPT_BASE(sp->id));
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#endif
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}
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/*
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* Read waitbase value from hw.
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*/
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static void syncpt_read_wait_base(struct host1x_syncpt *sp)
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{
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#if HOST1X_HW < 7
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struct host1x *host = sp->host;
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sp->base_val =
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host1x_sync_readl(host, HOST1X_SYNC_SYNCPT_BASE(sp->id));
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#endif
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}
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/*
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* Updates the last value read from hardware.
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*/
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static u32 syncpt_load(struct host1x_syncpt *sp)
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{
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struct host1x *host = sp->host;
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u32 old, live;
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/* Loop in case there's a race writing to min_val */
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do {
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old = host1x_syncpt_read_min(sp);
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live = host1x_sync_readl(host, HOST1X_SYNC_SYNCPT(sp->id));
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} while ((u32)atomic_cmpxchg(&sp->min_val, old, live) != old);
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if (!host1x_syncpt_check_max(sp, live))
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dev_err(host->dev,
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"%s failed: id=%u, name=%s, min=%d, max=%d, current process=%s\n",
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__func__, sp->id, sp->name,
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host1x_syncpt_read_min(sp), host1x_syncpt_read_max(sp),
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current->comm);
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return live;
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}
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/*
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* Write a cpu syncpoint increment to the hardware, without touching
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* the cache.
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*/
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static int syncpt_cpu_incr(struct host1x_syncpt *sp)
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{
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struct host1x *host = sp->host;
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u32 reg_offset = sp->id / 32;
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if (!host1x_syncpt_client_managed(sp) &&
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host1x_syncpt_idle(sp))
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return -EINVAL;
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host1x_sync_writel(host, BIT(sp->id % 32),
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HOST1X_SYNC_SYNCPT_CPU_INCR(reg_offset));
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wmb();
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return 0;
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}
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/**
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* syncpt_assign_to_channel() - Assign syncpoint to channel
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* @sp: syncpoint
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* @ch: channel
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*
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* On chips with the syncpoint protection feature (Tegra186+), assign @sp to
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* @ch, preventing other channels from incrementing the syncpoints. If @ch is
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* NULL, unassigns the syncpoint.
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*
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* On older chips, do nothing.
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*/
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static void syncpt_assign_to_channel(struct host1x_syncpt *sp,
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struct host1x_channel *ch)
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{
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#if HOST1X_HW >= 6
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struct host1x *host = sp->host;
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host1x_sync_writel(host,
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HOST1X_SYNC_SYNCPT_CH_APP_CH(ch ? ch->id : 0xff),
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HOST1X_SYNC_SYNCPT_CH_APP(sp->id));
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#if HOST1X_HW >= 9
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if (tegra_platform_is_vdk() && host->hv_regs)
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host1x_hypervisor_writel(host, 0x1, HOST1X_HV_SYNCPT_VM(sp->id));
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#endif
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#endif
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}
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/**
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* syncpt_enable_protection() - Enable syncpoint protection
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* @host: host1x instance
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*
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* On chips with the syncpoint protection feature (Tegra186+), enable this
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* feature. On older chips, do nothing.
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*/
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static void syncpt_enable_protection(struct host1x *host)
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{
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#if HOST1X_HW >= 6
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if (!host->hv_regs)
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return;
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host1x_hypervisor_writel(host, HOST1X_HV_SYNCPT_PROT_EN_CH_EN,
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HOST1X_HV_SYNCPT_PROT_EN);
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#endif
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}
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static const struct host1x_syncpt_ops host1x_syncpt_ops = {
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.restore = syncpt_restore,
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.restore_wait_base = syncpt_restore_wait_base,
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.load_wait_base = syncpt_read_wait_base,
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.load = syncpt_load,
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.cpu_incr = syncpt_cpu_incr,
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.assign_to_channel = syncpt_assign_to_channel,
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.enable_protection = syncpt_enable_protection,
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};
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