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d85d5d657d
Allow dev.h to be included from source directory. Bug 4164138 Bug 3682950 Change-Id: If6be232a428c843a45a14f155d957850d28847a9 Signed-off-by: Viswanath L <viswanathl@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/2979502 Reviewed-by: Sharad Gupta <sharadg@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
140 lines
3.1 KiB
C
140 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/**
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* Copyright (c) 2023, NVIDIA CORPORATION. All rights reserved.
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*/
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#include "dev.h"
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#include "dev-t264.h"
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#define AMISC_ADSP_CPU_CONFIG_STRIDE (0x1000)
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#define AMISC_ADSP_CPU_CONFIG (0x0)
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#define AMISC_ADSP_STATVECTORSEL (1 << 4)
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#define AMISC_ADSP_RUNSTALL (1 << 0)
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#define AMISC_ADSP_CPU_RESETVEC 0x4
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int nvadsp_os_t264_init(struct platform_device *pdev)
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{
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/* TBD */
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return 0;
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}
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#ifdef CONFIG_PM
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static int nvadsp_t264_clocks_disable(struct platform_device *pdev)
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{
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/* TBD */
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return 0;
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}
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static int nvadsp_t264_clocks_enable(struct platform_device *pdev)
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{
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/* TBD */
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return 0;
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}
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static int __nvadsp_t264_runtime_resume(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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int ret;
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dev_dbg(dev, "at %s:%d\n", __func__, __LINE__);
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ret = nvadsp_t264_clocks_enable(pdev);
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if (ret) {
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dev_dbg(dev, "failed in nvadsp_t264_clocks_enable\n");
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return ret;
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}
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return ret;
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}
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static int __nvadsp_t264_runtime_suspend(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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dev_dbg(dev, "at %s:%d\n", __func__, __LINE__);
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return nvadsp_t264_clocks_disable(pdev);
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}
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static int __nvadsp_t264_runtime_idle(struct device *dev)
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{
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dev_dbg(dev, "at %s:%d\n", __func__, __LINE__);
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return 0;
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}
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int nvadsp_pm_t264_init(struct platform_device *pdev)
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{
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struct nvadsp_drv_data *d = platform_get_drvdata(pdev);
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struct device *dev = &pdev->dev;
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dev_dbg(dev, "at %s:%d\n", __func__, __LINE__);
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d->runtime_suspend = __nvadsp_t264_runtime_suspend;
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d->runtime_resume = __nvadsp_t264_runtime_resume;
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d->runtime_idle = __nvadsp_t264_runtime_idle;
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return 0;
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}
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#endif /* CONFIG_PM */
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static int __set_boot_vec_t264(struct nvadsp_drv_data *d)
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{
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/* TBD */
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return 0;
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}
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static int __set_boot_freqs_t264(struct nvadsp_drv_data *d)
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{
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/* TBD */
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return 0;
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}
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static int __assert_t264_adsp(struct nvadsp_drv_data *d)
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{
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void __iomem *cpu_config_base;
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u32 cpu_config;
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/* TBD: CAR assert */
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/* Assert RUNSTALL */
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cpu_config_base = d->base_regs[AMISC] +
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(d->chip_data->adsp_prid * AMISC_ADSP_CPU_CONFIG_STRIDE);
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cpu_config = readl(cpu_config_base + AMISC_ADSP_CPU_CONFIG);
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cpu_config |= AMISC_ADSP_RUNSTALL;
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writel(cpu_config, cpu_config_base + AMISC_ADSP_CPU_CONFIG);
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return 0;
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}
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static int __deassert_t264_adsp(struct nvadsp_drv_data *d)
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{
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void __iomem *cpu_config_base;
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u32 cpu_config;
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/* TBD: CAR deassert */
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/* Deassert RUNSTALL */
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cpu_config_base = d->base_regs[AMISC] +
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(d->chip_data->adsp_prid * AMISC_ADSP_CPU_CONFIG_STRIDE);
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cpu_config = readl(cpu_config_base + AMISC_ADSP_CPU_CONFIG);
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cpu_config &= (~AMISC_ADSP_RUNSTALL);
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writel(cpu_config, cpu_config_base + AMISC_ADSP_CPU_CONFIG);
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return 0;
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}
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int nvadsp_reset_t264_init(struct platform_device *pdev)
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{
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struct nvadsp_drv_data *d = platform_get_drvdata(pdev);
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int ret = 0;
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d->assert_adsp = __assert_t264_adsp;
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d->deassert_adsp = __deassert_t264_adsp;
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d->adspall_rst = NULL; //TBD
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d->set_boot_vec = __set_boot_vec_t264;
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d->set_boot_freqs = __set_boot_freqs_t264;
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return ret;
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}
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