mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
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de5c7b0b06
Current code does not include IPC buffer region for Notification channel. This patch adds Notification IPC buffer size into total allocated buffer for IPC. This CL also increases Async IPC buffer frames from 1 to 4 Bug 3500242 Change-Id: I4ae07fdf9cf7c20fb70626698233f74a8b9fc8de Signed-off-by: Mahesh Kumar <mahkumar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2661833 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
194 lines
5.0 KiB
C
194 lines
5.0 KiB
C
/*
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* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef DCE_IPC_H
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#define DCE_IPC_H
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#include <dce-lock.h>
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#include <linux/tegra-ivc-instance.h>
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#include <linux/tegra-ivc.h>
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#include <interface/dce-admin-cmds.h>
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#include <interface/dce-core-interface-ipc-types.h>
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#include <interface/dce-ipc-state.h>
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#include <linux/platform/tegra/dce/dce-client-ipc.h>
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#define DCE_IPC_CHANNEL_TYPE_ADMIN 0U
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#define DCE_IPC_CHANNEL_TYPE_CPU_CLIENTS 1U
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#define DCE_IPC_MAX_IVC_CHANNELS 4U
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/**
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* TODO : Move the DispRM max to a config file
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*/
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#define DCE_DISPRM_CMD_MAX_NFRAMES 1U
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#define DCE_DISPRM_CMD_MAX_FSIZE 4096U
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#define DCE_DISPRM_EVENT_NOTIFY_CMD_MAX_NFRAMES 4U
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#define DCE_DISPRM_EVENT_NOTIFY_CMD_MAX_FSIZE 4096U
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#define DCE_ADMIN_CMD_MAX_FSIZE 1024U
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#define DCE_IPC_WAIT_TYPE_INVALID 0U
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#define DCE_IPC_WAIT_TYPE_SYNC 1U
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#define DCE_IPC_WAIT_TYPE_RPC 2U
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#define DCE_IPC_CHANNEL_VALID BIT(0)
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#define DCE_IPC_CHANNEL_INITIALIZED BIT(1)
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#define DCE_IPC_CHANNEL_SYNCED BIT(2)
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#define DCE_IPC_CHANNEL_MSG_HEADER BIT(15)
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#define DCE_IPC_CH_KMD_TYPE_ADMIN 0U
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#define DCE_IPC_CH_KMD_TYPE_RM 1U
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#define DCE_IPC_CH_KMD_TYPE_HDCP 2U
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#define DCE_IPC_CH_KMD_TYPE_RM_NOTIFY 3U
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#define DCE_IPC_CH_KMD_TYPE_MAX 4U
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/**
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* struct dce_ipc_signal - Stores ivc channel details
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*
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* @d : Pointer to struct tegra_dce.
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* @ibuff : Pointer to the input data buffer.
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* @obuff : Pointer to the output data buffer.
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* @d_ivc : Pointer to the ivc data structure.
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*/
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struct dce_ipc_mailbox {
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u8 mb_type;
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u32 mb_num;
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};
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/**
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* TODO : Use linux doorbell driver
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*/
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struct dce_ipc_doorbell {
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u32 db_num;
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u32 db_bit;
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};
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struct dce_ipc_signal_instance {
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u32 type;
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u32 sema_num;
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u32 sema_bit;
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union {
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struct dce_ipc_mailbox mbox;
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struct dce_ipc_doorbell db;
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} form;
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struct dce_ipc_signal *signal;
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struct dce_ipc_signal_instance *next;
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};
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typedef void (*dce_ipc_signal_notify)(struct tegra_dce *d,
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struct dce_ipc_signal_instance *signal);
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struct dce_ipc_signal {
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struct dce_ipc_channel *ch;
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dce_ipc_signal_notify notify;
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struct dce_ipc_signal_instance to_d;
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struct dce_ipc_signal_instance from_d;
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};
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int dce_ipc_signal_init(struct dce_ipc_channel *chan);
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/**
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* struct dce_ipc_region - Contains ivc region specific memory info.
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*
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* @size : total IVC region size.
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* @tx : transmit region info.
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* @rx : receive region info.
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*/
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struct dce_ipc_region {
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u32 s_offset;
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dma_addr_t iova;
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unsigned long size;
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void __iomem *base;
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};
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struct dce_ipc_queue_info {
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u8 nframes;
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u32 frame_sz;
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dma_addr_t rx_iova;
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dma_addr_t tx_iova;
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};
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/**
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* struct dce_ipc_channel - Stores ivc channel details
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*
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* @d : Pointer to struct tegra_dce.
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* @ibuff : Pointer to the input data buffer.
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* @obuff : Pointer to the output data buffer.
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* @d_ivc : Pointer to the ivc data structure.
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*/
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struct dce_ipc_channel {
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u32 flags;
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u32 w_type;
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u32 ch_type;
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u32 ipc_type;
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void *ibuff;
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void *obuff;
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struct ivc d_ivc;
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struct tegra_dce *d;
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struct dce_mutex lock;
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struct dce_ipc_signal signal;
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struct dce_ipc_queue_info q_info;
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};
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/**
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* struct dce_ipc - Stores ipc data
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*
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* @region - Store data about ivc region in DRAM
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* @ch - Array of pointers to store dce ivc channel info
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*/
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struct dce_ipc {
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struct dce_ipc_region region;
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struct dce_ipc_channel *ch[DCE_IPC_MAX_IVC_CHANNELS];
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};
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int dce_ipc_send_message(struct tegra_dce *d,
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u32 ch_type, const void *data, size_t size);
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int dce_ipc_read_message(struct tegra_dce *d,
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u32 ch_type, void *data, size_t size);
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int dce_ipc_send_message_sync(struct tegra_dce *d,
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u32 ch_type, struct dce_ipc_message *msg);
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int dce_ipc_get_channel_info(struct tegra_dce *d,
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struct dce_ipc_queue_info *q_info, u32 ch_index);
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void dce_ipc_free_region(struct tegra_dce *d);
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int dce_ipc_allocate_region(struct tegra_dce *d);
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struct tegra_dce *dce_ipc_get_dce_from_ch(u32 ch_type);
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int dce_ipc_channel_init(struct tegra_dce *d, u32 ch_type);
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void dce_ipc_channel_deinit(struct tegra_dce *d, u32 ch_type);
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void dce_ipc_channel_reset(struct tegra_dce *d, u32 ch_type);
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uint32_t dce_ipc_get_ipc_type(struct tegra_dce *d, u32 ch_type);
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bool dce_ipc_channel_is_ready(struct tegra_dce *d, u32 ch_type);
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bool dce_ipc_channel_is_synced(struct tegra_dce *d, u32 ch_type);
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u32 dce_ipc_get_cur_wait_type(struct tegra_dce *d, u32 ch_type);
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bool dce_ipc_is_data_available(struct tegra_dce *d, u32 ch_type);
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int dce_ipc_get_region_iova_info(struct tegra_dce *d, u64 *iova, u32 *size);
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int dce_ipc_init_signaling(struct tegra_dce *d, struct dce_ipc_channel *ch);
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void dce_ipc_deinit_signaling(struct tegra_dce *d, struct dce_ipc_channel *ch);
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#endif
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