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ef2e125868
- use TSC lock trigger interval param from dt to optimize As per HW suggestion we should not trigger sync on every PPS edge. TSC needs atleast 2 PPS edges to align with the PTP clock. - save platform specific register offset during drv init time instead of checking plat id everytime in monitoring thread Bug 5042311 Bug 4899241 Bug 5082436 Signed-off-by: Sheetal Tigadoli <stigadoli@nvidia.com> Change-Id: I22befbc2a52c22ace1a8573b9a34a544ed1ae8f9 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3294329 (cherry picked from commit 209dc26eddd2cd5e9d88ea8c6eb603706cd3c3f0) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3292322 Reviewed-by: Amlan Kundu <akundu@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>