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26b1cb4a82
- VIC RISC-V EB boot support - Programming sequence modification needed for Thor - Reloc block linear addressing not needed for t264 Bug 4132685 Signed-off-by: Santosh BS <santoshb@nvidia.com> Change-Id: I8ad47cce31cfd06020e33d3457a0d674a11e4d49
39 lines
980 B
C
39 lines
980 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015-2023, NVIDIA Corporation. All rights reserved.
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*/
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#ifndef TEGRA_VIC_H
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#define TEGRA_VIC_H
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/* VIC methods */
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#define VIC_SET_FCE_UCODE_SIZE 0x0000071C
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#define VIC_SET_FCE_UCODE_OFFSET 0x0000072C
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/* VIC registers */
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#define NV_PVIC_MISC_PRI_VIC_CG 0x000016d0
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#define CG_IDLE_CG_DLY_CNT(val) ((val & 0x3f) << 0)
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#define CG_IDLE_CG_EN (1 << 6)
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#define CG_WAKEUP_DLY_CNT(val) ((val & 0xf) << 16)
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#define VIC_TFBIF_ACTMON_ACTIVE_MASK_STARVED BIT(0)
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#define VIC_TFBIF_ACTMON_ACTIVE_MASK_STALLED BIT(1)
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#define VIC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED BIT(2)
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#define VIC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE BIT(7)
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/* Firmware offsets */
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#define VIC_UCODE_FCE_HEADER_OFFSET (6*4)
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#define VIC_UCODE_FCE_DATA_OFFSET (7*4)
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#define FCE_UCODE_SIZE_OFFSET (2*4)
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/*
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* VIC AXI read bus is 256-bits width
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* VIC AXI write bus is 256-bits width
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*/
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#define VIC_AXI_RW_BANDWIDTH 512
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#endif /* TEGRA_VIC_H */
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