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No need poll for SWR bit in DMA Basic Mode register for reading RO only registers after reset. Bug 2715328 Change-Id: Ib16c1d09386c00cdd98eadfb2fe6d9336d6de2b3 Signed-off-by: Bhadram Varka <vbhadram@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2220296 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>