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599d993c3d
Porting Base K5.10 driver to K5.15 Version: v5.9.0.3e_nv-1-gdafe03f15.20220505_COEX20200103-1717 Bug 3750163 Change-Id: I5c46db2976addff08a73bd31dafd84c093702545 Signed-off-by: Revanth Kumar Uppala <ruppala@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2814761 GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com> Reviewed-by: Narayan Reddy <narayanr@nvidia.com> Reviewed-by: Sushil Kumar Singh <sushilkumars@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
70 lines
2.2 KiB
C
70 lines
2.2 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef __PCI_OSINTF_H
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#define __PCI_OSINTF_H
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#ifdef RTK_129X_PLATFORM
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#define PCIE_SLOT1_MEM_START 0x9804F000
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#define PCIE_SLOT1_MEM_LEN 0x1000
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#define PCIE_SLOT1_CTRL_START 0x9804EC00
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#define PCIE_SLOT2_MEM_START 0x9803C000
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#define PCIE_SLOT2_MEM_LEN 0x1000
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#define PCIE_SLOT2_CTRL_START 0x9803BC00
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#define PCIE_MASK_OFFSET 0x100 /* mask offset from CTRL_START */
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#define PCIE_TRANSLATE_OFFSET 0x104 /* translate offset from CTRL_START */
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#endif
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#define PCI_BC_CLK_REQ BIT0
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#define PCI_BC_ASPM_L0s BIT1
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#define PCI_BC_ASPM_L1 BIT2
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#define PCI_BC_ASPM_L1Off BIT3
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//#define PCI_BC_ASPM_LTR BIT4
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//#define PCI_BC_ASPM_OBFF BIT5
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void PlatformClearPciPMEStatus(PADAPTER Adapter);
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void rtw_pci_aspm_config(_adapter *padapter);
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void rtw_pci_aspm_config_l1off_general(_adapter *padapter, u8 eanble);
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#ifdef CONFIG_64BIT_DMA
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u8 PlatformEnableDMA64(PADAPTER Adapter);
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#endif
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#ifdef CONFIG_PCI_DYNAMIC_ASPM
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void rtw_pci_set_aspm_lnkctl(_adapter *padapter, u8 mode);
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void rtw_pci_set_l1_latency(_adapter *padapter, u8 mode);
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static inline void rtw_pci_dynamic_aspm_set_mode(_adapter *padapter, u8 mode)
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{
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struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
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struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv);
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if (mode == pcipriv->aspm_mode)
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return;
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pcipriv->aspm_mode = mode;
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#ifdef CONFIG_PCI_DYNAMIC_ASPM_LINK_CTRL
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rtw_pci_set_aspm_lnkctl(padapter, mode);
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#endif
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#ifdef CONFIG_PCI_DYNAMIC_ASPM_L1_LATENCY
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rtw_pci_set_l1_latency(padapter, mode);
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#endif
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}
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#else
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#define rtw_pci_dynamic_aspm_set_mode(adapter, mode)
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#endif
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#endif
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