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git://nv-tegra.nvidia.com/linux-nv-oot.git
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c4ab6f5a0e
PEQ and MBDRC are sub blocks of OPE module. So far, these sub blocks were not represented by separate device nodes in DT. This has changed now where PEQ and MBDRC are children of OPE block. For now the driver structure is maintained as it is and explicitly parse PEQ and MBDRC nodes to create corresponding regmap interfaces. With this there is flexibility now to create separate device drivers for PEQ and MBDRC if necessary in future. Bug 3583581 Change-Id: I16ceb9b1a30b4ddb1a57fdef28db20c554c58b03 Signed-off-by: Sameer Pujar <spujar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2783022 Reviewed-by: Mohan Kumar D <mkumard@nvidia.com> Reviewed-by: Sharad Gupta <sharadg@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
104 lines
3.4 KiB
C
104 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* tegra210_ope.h - Definitions for Tegra210 OPE driver
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*
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* Copyright (c) 2014-2021 NVIDIA CORPORATION. All rights reserved.
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*
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*/
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#ifndef __TEGRA210_OPE_H__
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#define __TEGRA210_OPE_H__
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#include "tegra210_peq.h"
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/* Register offsets from TEGRA210_OPE*_BASE */
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/*
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* OPE_AXBAR_RX registers are with respect to AXBAR.
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* The data is coming from AXBAR to OPE for playback.
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*/
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#define TEGRA210_OPE_AXBAR_RX_STATUS 0xc
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#define TEGRA210_OPE_AXBAR_RX_INT_STATUS 0x10
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#define TEGRA210_OPE_AXBAR_RX_INT_MASK 0x14
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#define TEGRA210_OPE_AXBAR_RX_INT_SET 0x18
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#define TEGRA210_OPE_AXBAR_RX_INT_CLEAR 0x1c
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#define TEGRA210_OPE_AXBAR_RX_CIF_CTRL 0x20
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/*
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* OPE_AXBAR_TX registers are with respect to AXBAR.
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* The data is going out of OPE for playback.
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*/
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#define TEGRA210_OPE_AXBAR_TX_STATUS 0x4c
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#define TEGRA210_OPE_AXBAR_TX_INT_STATUS 0x50
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#define TEGRA210_OPE_AXBAR_TX_INT_MASK 0x54
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#define TEGRA210_OPE_AXBAR_TX_INT_SET 0x58
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#define TEGRA210_OPE_AXBAR_TX_INT_CLEAR 0x5c
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#define TEGRA210_OPE_AXBAR_TX_CIF_CTRL 0x60
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/* OPE Gloabal registers */
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#define TEGRA210_OPE_ENABLE 0x80
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#define TEGRA210_OPE_SOFT_RESET 0x84
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#define TEGRA210_OPE_CG 0x88
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#define TEGRA210_OPE_STATUS 0x8c
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#define TEGRA210_OPE_INT_STATUS 0x90
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#define TEGRA210_OPE_DIRECTION 0x94
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/* Fields for TEGRA210_OPE_ENABLE */
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#define TEGRA210_OPE_EN_SHIFT 0
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#define TEGRA210_OPE_EN (1 << TEGRA210_OPE_EN_SHIFT)
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/* Fields for TEGRA210_OPE_SOFT_RESET */
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#define TEGRA210_OPE_SOFT_RESET_SHIFT 0
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#define TEGRA210_OPE_SOFT_RESET_EN (1 << TEGRA210_OPE_SOFT_RESET_SHIFT)
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/* Fields for TEGRA210_OPE_DIRECTION */
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#define TEGRA210_OPE_DIRECTION_SHIFT 0
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#define TEGRA210_OPE_DIRECTION_MASK (1 << TEGRA210_OPE_DIRECTION_SHIFT)
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#define TEGRA210_OPE_DIRECTION_MBDRC_TO_PEQ (0 << TEGRA210_OPE_DIRECTION_SHIFT)
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#define TEGRA210_OPE_DIRECTION_PEQ_TO_MBDRC (1 << TEGRA210_OPE_DIRECTION_SHIFT)
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/* OPE register definitions end here */
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#define TEGRA210_PEQ_IORESOURCE_MEM 1
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#define TEGRA210_MBDRC_IORESOURCE_MEM 2
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struct tegra210_ope {
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struct regmap *regmap;
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struct regmap *peq_regmap;
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struct regmap *mbdrc_regmap;
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u32 peq_biquad_gains[TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH];
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u32 peq_biquad_shifts[TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH];
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};
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extern int tegra210_peq_regmap_init(struct platform_device *pdev);
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extern int tegra210_peq_codec_init(struct snd_soc_component *cmpnt);
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extern void tegra210_peq_restore(struct tegra210_ope *ope);
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extern void tegra210_peq_save(struct tegra210_ope *ope);
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extern int tegra210_mbdrc_regmap_init(struct platform_device *pdev);
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extern int tegra210_mbdrc_codec_init(struct snd_soc_component *cmpnt);
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extern int tegra210_mbdrc_hw_params(struct snd_soc_component *cmpnt);
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/* Extension of soc_bytes structure defined in sound/soc.h */
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struct tegra_soc_bytes {
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struct soc_bytes soc;
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u32 shift; /* Used as offset for ahub ram related programing */
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};
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/* Utility structures for using mixer control of type snd_soc_bytes */
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#define TEGRA_SOC_BYTES_EXT(xname, xbase, xregs, xshift, xmask, \
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xhandler_get, xhandler_put, xinfo) \
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{ \
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.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
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.name = xname, \
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.info = xinfo, \
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.get = xhandler_get, \
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.put = xhandler_put, \
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.private_value = ((unsigned long)&(struct tegra_soc_bytes) \
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{ \
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.soc.base = xbase, \
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.soc.num_regs = xregs, \
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.soc.mask = xmask, \
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.shift = xshift \
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}) \
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}
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#endif
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