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606f03fbf2
For T23x, we have a separate R5 based cluster named as Display Controller Engine(DCE) to run our Display RM code. This driver will run on CPU with the following functionality: Via debugfs for test and bring-up purposes: 1. Reads the DCE firmware image into DRAM. 2. Sets up DCE AST to cover the DCE firmware image. 3. Sets up R5 reset vector to point to DCE firmware entry point 4. Brings DCE out of reset 5. Dumps various regsiters for debug In production env: 1. Manages interrupts to CPU from DCE 2. Uses bootstrap command interface to define Admin IPC 3. Locks down bootstrap command interface 4. Uses Admin IPC to define message IPC 5. Uses Admin IPC to define message IPC payload area 6. Uses Admin IPC to set IPC channels 6. Uses Admin IPC to define crashdump area (optional) 7. Provides IPC interfaces for any DCE Client running on CCPLEX including Display RM. 8. Uses Admin IPC to set logging level (optional) This patch puts a framework in place with the following features : 1. Firmware Loading 2. AST Configuration 3. DCE Reset with EVP Programming 4. Logging Infra 5. Debugfs Support 6. Interrupt Handling 7. Mailbox Programming 8. IPC Programming 9. DCE Client Interface 10. Ftrace Support for debug purposes Change-Id: Idd28cd9254706c7313f531fcadaa7024a5b344e7 Signed-off-by: Arun Swain <arswain@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-t23x/+/2289865 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Mahesh Kumar <mahkumar@nvidia.com> Reviewed-by: Santosh Galma <galmar@nvidia.com> Reviewed-by: Mitch Luban <mluban@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Mahesh Kumar <mahkumar@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
67 lines
2.1 KiB
C
67 lines
2.1 KiB
C
/*
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef DCE_MAILBOX_H
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#define DCE_MAILBOX_H
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struct tegra_dce;
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#define DCE_MAILBOX_BOOT_INTERFACE 0U
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#define DCE_MAILBOX_ADMIN_INTERFACE 1U
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#define DCE_MAILBOX_DISPRM_INTERFACE 2U
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#define DCE_MAILBOX_MAX_INTERFACES 3U
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/**
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* struct dce_mailbox_interface - Contains dce mailbox interface state info
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*
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* @lock : dce_mutext for this mailbox interface.
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* @state : Stores the current status of the mailbox interface.
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* @ack_value : Stores the response received from dce f/w on an interface.
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* @s_mb : mailbox used to send commands to DCE CCPLEX for this interface.
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* @r_mb : mailbox used to receive commands from DCE for this interface.
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* @valid : true if the stored status is valid.
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*/
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struct dce_mailbox_interface {
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u8 s_mb;
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u8 r_mb;
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int state;
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bool valid;
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void *notify_data;
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struct dce_mutex lock;
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unsigned int ack_value;
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int (*dce_mailbox_wait)(struct tegra_dce *);
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void (*notify)(struct tegra_dce *, void *);
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};
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u32 dce_mailbox_get_interface_status(struct tegra_dce *d, u8 id);
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void dce_mailbox_store_interface_status(struct tegra_dce *d,
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u32 v, u8 id);
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void dce_mailbox_invalidate_status(struct tegra_dce *d, u8 id);
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void dce_mailbox_isr(struct tegra_dce *d);
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void dce_mailbox_set_full_interrupt(struct tegra_dce *d, u8 id);
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int dce_mailbox_send_cmd_sync(struct tegra_dce *d, u32 cmd, u32 interface);
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int dce_mailbox_init_interface(struct tegra_dce *d, u8 id, u8 s_mb,
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u8 r_mb, int (*dce_mailbox_wait)(struct tegra_dce *),
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void *notify_data, void (*notify)(struct tegra_dce *, void *));
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void dce_mailbox_deinit_interface(struct tegra_dce *d, u8 id);
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#endif
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