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606f03fbf2
For T23x, we have a separate R5 based cluster named as Display Controller Engine(DCE) to run our Display RM code. This driver will run on CPU with the following functionality: Via debugfs for test and bring-up purposes: 1. Reads the DCE firmware image into DRAM. 2. Sets up DCE AST to cover the DCE firmware image. 3. Sets up R5 reset vector to point to DCE firmware entry point 4. Brings DCE out of reset 5. Dumps various regsiters for debug In production env: 1. Manages interrupts to CPU from DCE 2. Uses bootstrap command interface to define Admin IPC 3. Locks down bootstrap command interface 4. Uses Admin IPC to define message IPC 5. Uses Admin IPC to define message IPC payload area 6. Uses Admin IPC to set IPC channels 6. Uses Admin IPC to define crashdump area (optional) 7. Provides IPC interfaces for any DCE Client running on CCPLEX including Display RM. 8. Uses Admin IPC to set logging level (optional) This patch puts a framework in place with the following features : 1. Firmware Loading 2. AST Configuration 3. DCE Reset with EVP Programming 4. Logging Infra 5. Debugfs Support 6. Interrupt Handling 7. Mailbox Programming 8. IPC Programming 9. DCE Client Interface 10. Ftrace Support for debug purposes Change-Id: Idd28cd9254706c7313f531fcadaa7024a5b344e7 Signed-off-by: Arun Swain <arswain@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-t23x/+/2289865 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Mahesh Kumar <mahkumar@nvidia.com> Reviewed-by: Santosh Galma <galmar@nvidia.com> Reviewed-by: Mitch Luban <mluban@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Mahesh Kumar <mahkumar@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
64 lines
1.8 KiB
C
64 lines
1.8 KiB
C
/*
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef DCE_UTIL_COMMON_H
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#define DCE_UTIL_COMMON_H
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#include <linux/types.h>
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#include <linux/bitops.h>
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#include <linux/bitmap.h>
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/**
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* This file contains all dce common fucntions and data strutcures which are
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* abstarcted out from the operating system. The underlying OS layer will
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* implement the pertinent low level details. This design is to make sure that
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* dce cpu driver can be leveraged across multiple OSes if the neede arises.
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*/
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struct tegra_dce;
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void dce_writel(struct tegra_dce *d, u32 r, u32 v);
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u32 dce_readl(struct tegra_dce *d, u32 r);
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void dce_writel_check(struct tegra_dce *d, u32 r, u32 v);
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bool dce_io_exists(struct tegra_dce *d);
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bool dce_io_valid_reg(struct tegra_dce *d, u32 r);
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struct dce_firmware *dce_request_firmware(struct tegra_dce *d,
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const char *fw_name);
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void dce_release_fw(struct tegra_dce *d, struct dce_firmware *fw);
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void *dce_kzalloc(struct tegra_dce *d, size_t size, bool dma_flag);
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void dce_kfree(struct tegra_dce *d, void *addr);
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unsigned long dce_get_nxt_pow_of_2(unsigned long *addr, u8 nbits);
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static inline void dce_bitmap_set(unsigned long *map,
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unsigned int start, unsigned int len)
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{
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bitmap_set(map, start, (int)len);
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}
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static inline void dce_bitmap_clear(unsigned long *map,
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unsigned int start, unsigned int len)
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{
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bitmap_clear(map, start, (int)len);
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}
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#endif
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