mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
synced 2025-12-22 09:11:26 +03:00
ec0813dbd1
Following AHUB modules are considered as part of this series. This updates all drivers to use component structure. Initially AHUB, I2S, DMIC, DSPK and ADMAIF drivers were updated. FPGA code is removed from the related drivers. This can be cherry-picked if it is really required. Bug 2845498 Change-Id: Ia3f60257c225d281d86ad83325fb517969259cb4 Signed-off-by: Sameer Pujar <spujar@nvidia.com>
396 lines
10 KiB
C
396 lines
10 KiB
C
/*
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* tegra210_ope.c - Tegra210 OPE driver
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*
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* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <linux/of_device.h>
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#include "tegra210_ahub.h"
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#include "tegra210_ope.h"
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#include "tegra_cif.h"
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#define DRV_NAME "tegra210-ope"
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static const struct reg_default tegra210_ope_reg_defaults[] = {
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{ TEGRA210_OPE_AXBAR_RX_INT_MASK, 0x00000001},
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{ TEGRA210_OPE_AXBAR_RX_CIF_CTRL, 0x00007700},
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{ TEGRA210_OPE_AXBAR_TX_INT_MASK, 0x00000001},
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{ TEGRA210_OPE_AXBAR_TX_CIF_CTRL, 0x00007700},
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{ TEGRA210_OPE_CG, 0x1},
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};
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static int tegra210_ope_runtime_suspend(struct device *dev)
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{
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struct tegra210_ope *ope = dev_get_drvdata(dev);
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tegra210_peq_save(ope);
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regcache_cache_only(ope->mbdrc_regmap, true);
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regcache_cache_only(ope->peq_regmap, true);
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regcache_cache_only(ope->regmap, true);
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regcache_mark_dirty(ope->regmap);
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regcache_mark_dirty(ope->peq_regmap);
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regcache_mark_dirty(ope->mbdrc_regmap);
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return 0;
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}
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static int tegra210_ope_runtime_resume(struct device *dev)
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{
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struct tegra210_ope *ope = dev_get_drvdata(dev);
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regcache_cache_only(ope->regmap, false);
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regcache_cache_only(ope->peq_regmap, false);
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regcache_cache_only(ope->mbdrc_regmap, false);
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regcache_sync(ope->regmap);
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regcache_sync(ope->peq_regmap);
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regcache_sync(ope->mbdrc_regmap);
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tegra210_peq_restore(ope);
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return 0;
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}
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static int tegra210_ope_set_audio_cif(struct tegra210_ope *ope,
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struct snd_pcm_hw_params *params,
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unsigned int reg)
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{
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int channels, audio_bits;
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struct tegra_cif_conf cif_conf;
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memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
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channels = params_channels(params);
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if (channels < 2)
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return -EINVAL;
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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audio_bits = TEGRA_ACIF_BITS_16;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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audio_bits = TEGRA_ACIF_BITS_32;
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break;
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default:
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return -EINVAL;
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}
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cif_conf.audio_ch = channels;
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cif_conf.client_ch = channels;
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cif_conf.audio_bits = audio_bits;
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cif_conf.client_bits = audio_bits;
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tegra_set_cif(ope->regmap, reg, &cif_conf);
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return 0;
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}
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static int tegra210_ope_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct device *dev = dai->dev;
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struct tegra210_ope *ope = snd_soc_dai_get_drvdata(dai);
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int ret;
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/* set RX cif and TX cif */
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ret = tegra210_ope_set_audio_cif(ope, params,
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TEGRA210_OPE_AXBAR_RX_CIF_CTRL);
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if (ret) {
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dev_err(dev, "Can't set OPE RX CIF: %d\n", ret);
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return ret;
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}
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ret = tegra210_ope_set_audio_cif(ope, params,
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TEGRA210_OPE_AXBAR_TX_CIF_CTRL);
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if (ret) {
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dev_err(dev, "Can't set OPE TX CIF: %d\n", ret);
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return ret;
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}
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tegra210_mbdrc_hw_params(dai->component);
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return ret;
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}
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static int tegra210_ope_codec_probe(struct snd_soc_component *cmpnt)
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{
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tegra210_peq_codec_init(cmpnt);
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tegra210_mbdrc_codec_init(cmpnt);
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return 0;
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}
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static struct snd_soc_dai_ops tegra210_ope_dai_ops = {
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.hw_params = tegra210_ope_hw_params,
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};
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static struct snd_soc_dai_driver tegra210_ope_dais[] = {
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{
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.name = "OPE IN",
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.playback = {
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.stream_name = "OPE Receive",
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.channels_min = 1,
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.channels_max = 8,
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.rates = SNDRV_PCM_RATE_8000_192000,
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.formats = SNDRV_PCM_FMTBIT_S8 |
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SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S32_LE,
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},
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},
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{
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.name = "OPE OUT",
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.capture = {
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.stream_name = "OPE Transmit",
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.channels_min = 1,
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.channels_max = 8,
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.rates = SNDRV_PCM_RATE_8000_192000,
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.formats = SNDRV_PCM_FMTBIT_S8 |
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SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S32_LE,
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},
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.ops = &tegra210_ope_dai_ops,
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}
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};
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static const struct snd_soc_dapm_widget tegra210_ope_widgets[] = {
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SND_SOC_DAPM_AIF_IN("OPE RX", NULL, 0, SND_SOC_NOPM,
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0, 0),
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SND_SOC_DAPM_AIF_OUT("OPE TX", NULL, 0, TEGRA210_OPE_ENABLE,
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TEGRA210_OPE_EN_SHIFT, 0),
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};
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static const struct snd_soc_dapm_route tegra210_ope_routes[] = {
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{ "OPE RX", NULL, "OPE Receive" },
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{ "OPE TX", NULL, "OPE RX" },
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{ "OPE Transmit", NULL, "OPE TX" },
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};
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static const struct snd_kcontrol_new tegra210_ope_controls[] = {
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SOC_SINGLE("direction peq to mbdrc", TEGRA210_OPE_DIRECTION,
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TEGRA210_OPE_DIRECTION_SHIFT, 1, 0),
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};
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static struct snd_soc_component_driver tegra210_ope_cmpnt = {
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.probe = tegra210_ope_codec_probe,
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.dapm_widgets = tegra210_ope_widgets,
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.num_dapm_widgets = ARRAY_SIZE(tegra210_ope_widgets),
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.dapm_routes = tegra210_ope_routes,
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.num_dapm_routes = ARRAY_SIZE(tegra210_ope_routes),
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.controls = tegra210_ope_controls,
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.num_controls = ARRAY_SIZE(tegra210_ope_controls),
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};
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static bool tegra210_ope_wr_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA210_OPE_AXBAR_RX_INT_MASK:
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case TEGRA210_OPE_AXBAR_RX_INT_SET:
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case TEGRA210_OPE_AXBAR_RX_INT_CLEAR:
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case TEGRA210_OPE_AXBAR_RX_CIF_CTRL:
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case TEGRA210_OPE_AXBAR_TX_INT_MASK:
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case TEGRA210_OPE_AXBAR_TX_INT_SET:
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case TEGRA210_OPE_AXBAR_TX_INT_CLEAR:
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case TEGRA210_OPE_AXBAR_TX_CIF_CTRL:
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case TEGRA210_OPE_ENABLE:
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case TEGRA210_OPE_SOFT_RESET:
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case TEGRA210_OPE_CG:
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case TEGRA210_OPE_DIRECTION:
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return true;
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default:
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return false;
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};
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}
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static bool tegra210_ope_rd_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA210_OPE_AXBAR_RX_STATUS:
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case TEGRA210_OPE_AXBAR_RX_INT_STATUS:
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case TEGRA210_OPE_AXBAR_RX_INT_MASK:
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case TEGRA210_OPE_AXBAR_RX_INT_SET:
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case TEGRA210_OPE_AXBAR_RX_INT_CLEAR:
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case TEGRA210_OPE_AXBAR_RX_CIF_CTRL:
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case TEGRA210_OPE_AXBAR_TX_STATUS:
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case TEGRA210_OPE_AXBAR_TX_INT_STATUS:
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case TEGRA210_OPE_AXBAR_TX_INT_MASK:
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case TEGRA210_OPE_AXBAR_TX_INT_SET:
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case TEGRA210_OPE_AXBAR_TX_INT_CLEAR:
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case TEGRA210_OPE_AXBAR_TX_CIF_CTRL:
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case TEGRA210_OPE_ENABLE:
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case TEGRA210_OPE_SOFT_RESET:
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case TEGRA210_OPE_CG:
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case TEGRA210_OPE_STATUS:
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case TEGRA210_OPE_INT_STATUS:
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case TEGRA210_OPE_DIRECTION:
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return true;
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default:
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return false;
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};
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}
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static bool tegra210_ope_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA210_OPE_AXBAR_RX_STATUS:
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case TEGRA210_OPE_AXBAR_RX_INT_SET:
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case TEGRA210_OPE_AXBAR_RX_INT_STATUS:
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case TEGRA210_OPE_AXBAR_TX_STATUS:
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case TEGRA210_OPE_AXBAR_TX_INT_SET:
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case TEGRA210_OPE_AXBAR_TX_INT_STATUS:
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case TEGRA210_OPE_SOFT_RESET:
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case TEGRA210_OPE_STATUS:
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case TEGRA210_OPE_INT_STATUS:
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return true;
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default:
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return false;
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};
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}
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static const struct regmap_config tegra210_ope_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = TEGRA210_OPE_DIRECTION,
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.writeable_reg = tegra210_ope_wr_reg,
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.readable_reg = tegra210_ope_rd_reg,
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.volatile_reg = tegra210_ope_volatile_reg,
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.reg_defaults = tegra210_ope_reg_defaults,
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.num_reg_defaults = ARRAY_SIZE(tegra210_ope_reg_defaults),
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.cache_type = REGCACHE_FLAT,
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};
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static const struct of_device_id tegra210_ope_of_match[] = {
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{ .compatible = "nvidia,tegra210-ope" },
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{},
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};
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static int tegra210_ope_platform_probe(struct platform_device *pdev)
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{
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struct tegra210_ope *ope;
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struct resource *mem;
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void __iomem *regs;
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int ret = 0;
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const struct of_device_id *match;
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pr_info("OPE platform probe\n");
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match = of_match_device(tegra210_ope_of_match, &pdev->dev);
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if (!match) {
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dev_err(&pdev->dev, "Error: No device match found\n");
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return -ENODEV;
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}
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ope = devm_kzalloc(&pdev->dev, sizeof(*ope), GFP_KERNEL);
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if (!ope)
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return -ENOMEM;
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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regs = devm_ioremap_resource(&pdev->dev, mem);
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if (IS_ERR(regs))
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return PTR_ERR(regs);
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ope->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
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&tegra210_ope_regmap_config);
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if (IS_ERR(ope->regmap)) {
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dev_err(&pdev->dev, "regmap init failed\n");
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return PTR_ERR(ope->regmap);
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}
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regcache_cache_only(ope->regmap, true);
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dev_set_drvdata(&pdev->dev, ope);
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ret = tegra210_peq_init(pdev, TEGRA210_PEQ_IORESOURCE_MEM);
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if (ret < 0) {
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dev_err(&pdev->dev, "peq init failed\n");
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return ret;
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}
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regcache_cache_only(ope->peq_regmap, true);
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ret = tegra210_mbdrc_init(pdev, TEGRA210_MBDRC_IORESOURCE_MEM);
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if (ret < 0) {
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dev_err(&pdev->dev, "mbdrc init failed\n");
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return ret;
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}
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regcache_cache_only(ope->mbdrc_regmap, true);
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pm_runtime_enable(&pdev->dev);
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ret = snd_soc_register_component(&pdev->dev, &tegra210_ope_cmpnt,
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tegra210_ope_dais,
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ARRAY_SIZE(tegra210_ope_dais));
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if (ret != 0) {
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dev_err(&pdev->dev, "Could not register CODEC: %d\n", ret);
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pm_runtime_disable(&pdev->dev);
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return ret;
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}
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pr_info("OPE platform probe successful\n");
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return 0;
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}
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static int tegra210_ope_platform_remove(struct platform_device *pdev)
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{
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snd_soc_unregister_component(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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if (!pm_runtime_status_suspended(&pdev->dev))
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tegra210_ope_runtime_suspend(&pdev->dev);
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return 0;
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}
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static const struct dev_pm_ops tegra210_ope_pm_ops = {
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SET_RUNTIME_PM_OPS(tegra210_ope_runtime_suspend,
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tegra210_ope_runtime_resume, NULL)
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SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
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pm_runtime_force_resume)
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};
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static struct platform_driver tegra210_ope_driver = {
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.driver = {
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.name = DRV_NAME,
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.owner = THIS_MODULE,
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.of_match_table = tegra210_ope_of_match,
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.pm = &tegra210_ope_pm_ops,
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},
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.probe = tegra210_ope_platform_probe,
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.remove = tegra210_ope_platform_remove,
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};
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module_platform_driver(tegra210_ope_driver)
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MODULE_AUTHOR("Sumit Bhattacharya <sumitb@nvidia.com>");
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MODULE_DESCRIPTION("Tegra210 OPE ASoC driver");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:" DRV_NAME);
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MODULE_DEVICE_TABLE(of, tegra210_ope_of_match);
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