Mikko Perttunen ec4681358b drm/tegra: nvdec: Enable SLCG/PG ...

Add register writes to enable second level clock gating /
power gating. For now only for Tegra234.

Bug 4475968

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Change-Id: Ie2e3b6d375bb6b7772b71999df81d73bea7ad550
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3116201
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Santosh BS <santoshb@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>

2024-07-30 08:52:07 -07:00

..

tegra

drm/tegra: nvdec: Enable SLCG/PG

2024-07-30 08:52:07 -07:00