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cbf177852b
Add IP-HWPM interface in NVENC, OFA and VIC drivers. This code will - register with HWPM driver during probe - expose power management and register read/write function. Bug 4158030 Change-Id: I9311c9fc31cffadf11c36b6e4516f0da84dcbdf4 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2954070 Reviewed-by: Santosh BS <santoshb@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
117 lines
3.0 KiB
C
117 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA Corporation.
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*/
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/io.h>
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#include <uapi/linux/tegra-soc-hwpm-uapi.h>
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#include "hwpm.h"
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#ifdef CONFIG_TEGRA_SYSTEM_TYPE_ACK
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void tegra_drm_hwpm_register(struct tegra_drm_hwpm *drm_hwpm, u64 resource_base,
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enum tegra_drm_hwpm_ip hwpm_ip)
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{
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}
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void tegra_drm_hwpm_unregister(struct tegra_drm_hwpm *drm_hwpm, u64 resource_base,
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enum tegra_drm_hwpm_ip hwpm_ip)
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{
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}
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#else
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static u32 tegra_drm_hwpm_readl(struct tegra_drm_hwpm *hwpm, u32 offset)
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{
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return readl(hwpm->regs + offset);
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}
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static void tegra_drm_hwpm_writel(struct tegra_drm_hwpm *hwpm, u32 value, u32 offset)
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{
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writel(value, hwpm->regs + offset);
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}
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static int tegra_drm_hwpm_ip_pm(void *ip_dev, bool disable)
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{
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int err = 0;
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struct tegra_drm_hwpm *hwpm = (struct tegra_drm_hwpm *)ip_dev;
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if (disable) {
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err = pm_runtime_resume_and_get(hwpm->dev);
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if (err < 0) {
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dev_err(hwpm->dev, "runtime resume failed %d", err);
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}
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} else {
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err = pm_runtime_put_autosuspend(hwpm->dev);
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if (err < 0) {
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dev_err(hwpm->dev, "runtime suspend failed %d", err);
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}
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}
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return err;
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}
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static int tegra_drm_hwpm_ip_reg_op(void *ip_dev,
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enum tegra_soc_hwpm_ip_reg_op reg_op,
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u32 inst_element_index, u64 reg_offset, u32 *reg_data)
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{
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struct tegra_drm_hwpm *hwpm = (struct tegra_drm_hwpm *)ip_dev;
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if (reg_op == TEGRA_SOC_HWPM_IP_REG_OP_READ) {
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*reg_data = tegra_drm_hwpm_readl(hwpm, reg_offset);
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} else if (reg_op == TEGRA_SOC_HWPM_IP_REG_OP_WRITE) {
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tegra_drm_hwpm_writel(hwpm, *reg_data, reg_offset);
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}
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return 0;
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}
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static u32 tegra_drm_hwpm_get_resource_index(enum tegra_drm_hwpm_ip hwpm_ip)
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{
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switch (hwpm_ip) {
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case TEGRA_DRM_HWPM_IP_OFA:
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return TEGRA_SOC_HWPM_RESOURCE_OFA;
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break;
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case TEGRA_DRM_HWPM_IP_NVDEC:
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return TEGRA_SOC_HWPM_RESOURCE_NVDEC;
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break;
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case TEGRA_DRM_HWPM_IP_NVENC:
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return TEGRA_SOC_HWPM_RESOURCE_NVENC;
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break;
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case TEGRA_DRM_HWPM_IP_VIC:
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return TEGRA_SOC_HWPM_RESOURCE_VIC;
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break;
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case TEGRA_DRM_HWPM_IP_INVALID:
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default:
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return TERGA_SOC_HWPM_NUM_RESOURCES;
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break;
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}
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}
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void tegra_drm_hwpm_register(struct tegra_drm_hwpm *drm_hwpm, u64 resource_base,
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enum tegra_drm_hwpm_ip hwpm_ip)
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{
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struct tegra_soc_hwpm_ip_ops hwpm_ip_ops;
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hwpm_ip_ops.ip_dev = (void *)drm_hwpm;
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hwpm_ip_ops.ip_base_address = resource_base;
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hwpm_ip_ops.resource_enum = tegra_drm_hwpm_get_resource_index(hwpm_ip);
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hwpm_ip_ops.hwpm_ip_pm = &tegra_drm_hwpm_ip_pm;
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hwpm_ip_ops.hwpm_ip_reg_op = &tegra_drm_hwpm_ip_reg_op;
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tegra_soc_hwpm_ip_register(&hwpm_ip_ops);
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}
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void tegra_drm_hwpm_unregister(struct tegra_drm_hwpm *drm_hwpm, u64 resource_base,
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enum tegra_drm_hwpm_ip hwpm_ip)
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{
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struct tegra_soc_hwpm_ip_ops hwpm_ip_ops;
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hwpm_ip_ops.ip_dev = (void *)drm_hwpm;
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hwpm_ip_ops.ip_base_address = resource_base;
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hwpm_ip_ops.resource_enum = tegra_drm_hwpm_get_resource_index(hwpm_ip);
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tegra_soc_hwpm_ip_unregister(&hwpm_ip_ops);
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}
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#endif
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