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d61f30d568
Bug 3680143 Change-Id: I1092b85239222b6af9a9ecfc536801f298706e60 Signed-off-by: Sanjay Chandrashekara <sanjayc@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2774586 Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
92 lines
3.4 KiB
C
92 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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#ifndef T23X_ARI_H
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#define T23X_ARI_H
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/* ARI Version numbers */
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#define TEGRA_ARI_VERSION_MAJOR 8UL
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#define TEGRA_ARI_VERSION_MINOR 1UL
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/*
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* ARI Request IDs
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*
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* TODO: RENUMBER range before finalization
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* NOTE: for documentation purposes, only documenting gaps
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* in ranges, to indicate that we know about the missing ids
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*
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* Require NO LAB Locks
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* range from 0 - 31
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*/
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#define TEGRA_ARI_VERSION 0UL
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#define TEGRA_ARI_ECHO 1UL
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#define TEGRA_ARI_NUM_CORES 2UL
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#define TEGRA_ARI_CSTATE_STAT_QUERY 3UL
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/* Undefined 4 - 28 */
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/* Debug Only ARIs at the end of the NO LAB Lock Range */
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#define TEGRA_ARI_CORE_DEBUG_RECOVERY 29UL
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#define TEGRA_ARI_DSU_DEBUG_RECOVERY 30UL
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#define TEGRA_ARI_CLUSTER_WARM_RESET 31UL
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/*
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* Require CORE LAB Lock -- obtained by MTM from ARI
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* range from 32 - 63
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*/
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/* UNDEFINED 32 */
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/* UNDEFINED 33 */
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#define TEGRA_ARI_ONLINE_CORE 34UL
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#define TEGRA_ARI_ENTER_CSTATE 35UL
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/* UNDEFINED 36 */
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#define TEGRA_ARI_TRIGGER_ONLINE_IST 37UL
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/*
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* Require CLUSTER and CORE LAB Lock -- obtained by MTM from ARI
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* range from 64 - 95
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*/
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/* UNDEFINED 64 */
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#define TEGRA_ARI_NVFREQ_REQ 65UL
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#define TEGRA_ARI_NVFREQ_FEEDBACK 66UL
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#define TEGRA_ARI_CLUSTER_ATCLKEN 67UL
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/*
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* Require CCPLEX, CLUSTER and CORE LAB Lock -- obtained by MTM from ARI
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* range from 96 - 127
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*/
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#define TEGRA_ARI_CCPLEX_CACHE_CONTROL 96UL
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#define TEGRA_ARI_CCPLEX_CACHE_CLEAN 97UL
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/* UNDEFINED 98 */
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#define TEGRA_ARI_CCPLEX_LATIC_ON 99UL
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#define TEGRA_ARI_UPDATE_CROSSOVER 100UL
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/* UNDEFINED 101 */
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#define TEGRA_ARI_CCPLEX_SHUTDOWN 102UL
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/* UNDEFINED 103 */
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#define TEGRA_ARI_CSTATE_INFO 104UL
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#define TEGRA_ARI_IS_SC7_ALLOWED 105UL
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/* UNDEFINED 106 */
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/* UNDEFINED 107 */
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#define TEGRA_ARI_SECURITY_CONFIG 108UL
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#define TEGRA_ARI_UPDATE_CCPLEX_CARVEOUTS 109UL
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#define TEGRA_ARI_DDA_CONTROL 110UL
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#define TEGRA_ARI_PERFMON 111UL
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#define TEGRA_ARI_DEBUG_CONFIG 112UL
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#define TEGRA_ARI_CCPLEX_ERROR_RECOVERY_RESET 114UL
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/* Values for ARI CSTATE STAT QUERY */
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#define TEGRA_ARI_STAT_QUERY_SC7_ENTRIES 1UL
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#define TEGRA_ARI_STAT_QUERY_CC7_ENTRIES 6UL
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#define TEGRA_ARI_STAT_QUERY_C7_ENTRIES 14UL
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#define TEGRA_ARI_STAT_QUERY_SC7_ENTRY_TIME_SUM 60UL
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#define TEGRA_ARI_STAT_QUERY_CC7_ENTRY_TIME_SUM 61UL
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#define TEGRA_ARI_STAT_QUERY_C7_ENTRY_TIME_SUM 64UL
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#define TEGRA_ARI_STAT_QUERY_SC7_EXIT_TIME_SUM 70UL
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#define TEGRA_ARI_STAT_QUERY_CC7_EXIT_TIME_SUM 71UL
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#define TEGRA_ARI_STAT_QUERY_C7_EXIT_TIME_SUM 74UL
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/* Values for ARI UPDATE CROSSOVER */
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#define TEGRA_ARI_CROSSOVER_C7_LOWER_BOUND 0UL
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#define TEGRA_ARI_CROSSOVER_CC7_LOWER_BOUND 1UL
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/* Values for ARI UPDATE CCPLEX CARVEOUTS */
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#define TEGRA_ARI_UPDATE_CCPLEX_CARVEOUTS_ALL 0UL
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#endif /* T23X_ARI_H */
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