mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
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ef3f18c398
This patch removes unnecessary dce_info prints to avoid flooding of uart logs. JIRA TDS-5691 Change-Id: I9c9a32815e685504b443f24483502fe019ac0eaf Signed-off-by: Mahesh Kumar <mahkumar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-t23x/+/2375553 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Santosh Galma <galmar@nvidia.com> Reviewed-by: Arun Swain <arswain@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
747 lines
17 KiB
C
747 lines
17 KiB
C
/*
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <dce.h>
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#include <dce-util-common.h>
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#include <interface/dce-interface.h>
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#include <interface/dce-boot-cmds.h>
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#include <interface/dce-interface.h>
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/**
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* dce_boot_complete - Checks if dce has complelted boot.
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*
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* @d - Pointer to tegra_dce struct.
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*
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* Return : True if boot is complete
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*/
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static inline bool dce_boot_complete(struct tegra_dce *d)
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{
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return !!(dce_ss_get_state(d, DCE_BOOT_SEMA)
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& DCE_BOOT_COMPLETE);
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}
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/**
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* dce_boot_poll_boot_complete - Poll until dce boot is complete.
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*
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* @d : Pointer to tegra_dce struct.
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*
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* Return : 0 if successful
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*/
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static int dce_boot_poll_boot_complete(struct tegra_dce *d)
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{
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int ret = 0;
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while (!dce_boot_complete(d)) {
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dce_worker_thread_wait(d,
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EVENT_ID_DCE_BOOT_COMPLETE_IRQ_REQ_SET);
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}
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if (dce_worker_get_state(d) == STATE_DCE_WORKER_ABORTED)
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ret = -1;
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return ret;
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}
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/**
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* dce_req_boot_irq_sync - Requests DCE to raise an
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* interrupt on boot completion.
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*
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* @d - Pointer to tegra_dce struct.
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*
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* Return : 0 if sucessful.
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*/
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static int dce_req_boot_irq_sync(struct tegra_dce *d)
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{
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int ret = 0;
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#define DCE_BOOT_INIT_BPOS 31U
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dce_ss_set(d, DCE_BOOT_INIT_BPOS, DCE_BOOT_SEMA);
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#undef DCE_BOOT_INIT_BPOS
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dce_info(d, "Waiting on dce fw to boot...");
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ret = dce_boot_poll_boot_complete(d);
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if (ret)
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dce_err(d, "DCE Boot Complete Poll Interrupted");
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return ret;
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}
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/**
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* dce_wait_boot_complete - Wait for the DCE to boot and be ready to receive
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* commands from CCPLEX driver.
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*
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* @d : Pointer to tegra_dce struct.
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*
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* Return : 0 if successful
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*/
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int dce_wait_boot_complete(struct tegra_dce *d)
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{
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int ret = 0;
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if (dce_boot_complete(d))
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goto boot_done;
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ret = dce_req_boot_irq_sync(d);
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boot_done:
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if (!ret) {
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dce_set_boot_complete(d, true);
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d->boot_status |= DCE_FW_EARLY_BOOT_DONE;
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dce_info(d, "dce is ready to receive bootstrap commands");
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} else {
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d->boot_status |= DCE_FW_EARLY_BOOT_FAILED;
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}
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return ret;
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}
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/**
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* dce_handle_irq_status - Handles irq status from DCE
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*
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* @d : Pointer to struct tegra_dce
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* @status : Status received from DCE
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*
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* Return : Void
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*/
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void dce_handle_irq_status(struct tegra_dce *d, u32 status)
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{
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enum dce_worker_event_id_type event;
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if (status & DCE_IRQ_LOG_OVERFLOW)
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dce_info(d, "DCE trace log overflow error received");
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if (status & DCE_IRQ_LOG_READY)
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dce_info(d, "DCE trace log buffers available");
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if (status & DCE_IRQ_CRASH_LOG)
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dce_info(d, "DCE crash log available");
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if (status & DCE_IRQ_ABORT)
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dce_err(d, "DCE ucode abort occurred");
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if (status & DCE_IRQ_SC7_ENTERED)
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dce_info(d, "DCE can be safely powered-off now");
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event = EVENT_ID_DCE_INTERFACE_ERROR_RECEIVED;
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if (status & DCE_IRQ_READY) {
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dce_info(d, "DCE IRQ Ready Received");
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event = EVENT_ID_DCE_BOOT_COMPLETE_IRQ_RECEIVED;
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}
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dce_worker_thread_wakeup(d, event);
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}
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/**
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* dce_bootstrap_handle_boot_status- Handles boot status from DCE
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*
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* @d : Pointer to struct tegra_dce
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* @status : Status received from DCE
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*
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* Return : Void
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*/
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void dce_bootstrap_handle_boot_status(struct tegra_dce *d, u32 status)
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{
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enum dce_worker_event_id_type event;
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event = EVENT_ID_DCE_IPC_SIGNAL_RECEIVED;
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dce_mailbox_store_interface_status(d, status,
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DCE_MAILBOX_BOOT_INTERFACE);
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dce_worker_thread_wakeup(d, event);
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}
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/**
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* dce_boot_interface_isr - Isr for the CCPLEX<->DCE boot interface.
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*
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* @d : Pointer to tegra_dce struct.
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*
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* Return : Void
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*/
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static void dce_boot_interface_isr(struct tegra_dce *d, void *data)
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{
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u32 status;
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u8 interface_id = DCE_MAILBOX_BOOT_INTERFACE;
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status = dce_mailbox_get_interface_status(d, interface_id);
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if (status == 0xffffffff)
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return;
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switch (DCE_IRQ_GET_STATUS_TYPE(status)) {
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case DCE_IRQ_STATUS_TYPE_IRQ:
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dce_handle_irq_status(d, status);
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break;
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case DCE_IRQ_STATUS_TYPE_BOOT_CMD:
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dce_bootstrap_handle_boot_status(d, status);
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break;
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default:
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dce_info(d, "Invalid Status Received from DCE. Status: [%x]",
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status);
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break;
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}
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}
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/**
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* dce_parse_boot_status_err - Parses the error sent by DCE
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*
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* @d : Pointer to struct tegra_dce
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* @status : Status read from mailbox
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*
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* Return : Void
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*/
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static void dce_parse_boot_status_err(struct tegra_dce *d, u32 status)
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{
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#define DCE_BOOT_ERR_MASK 0x7FFFFF
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status &= DCE_BOOT_ERR_MASK;
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#undef DCE_BOOT_ERR_MASK
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switch (status) {
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case DCE_BOOT_CMD_ERR_BAD_COMMAND:
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dce_info(d, "Boot Status Error : DCE_BOOT_CMD_ERR_BAD_COMMAND");
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break;
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case DCE_BOOT_CMD_ERR_UNIMPLEMENTED:
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dce_info(d, "Boot Status Error : DCE_BOOT_CMD_ERR_UNIMPLEMENTED");
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break;
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case DCE_BOOT_CMD_ERR_IPC_SETUP:
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dce_info(d, "Boot Status Error : DCE_BOOT_CMD_ERR_IPC_SETUP");
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break;
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case DCE_BOOT_CMD_ERR_INVALID_NFRAMES:
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dce_info(d, "Boot Status Error : DCE_BOOT_CMD_ERR_INVALID_NFRAMES");
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break;
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case DCE_BOOT_CMD_ERR_IPC_CREATE:
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dce_info(d, "Boot Status Error : DCE_BOOT_CMD_ERR_IPC_CREATE");
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break;
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case DCE_BOOT_CMD_ERR_LOCKED:
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dce_info(d, "Boot Status Error : DCE_BOOT_CMD_ERR_LOCKED");
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break;
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default:
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dce_info(d, "Invalid Error Status Rcvd. Status: [%x]", status);
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break;
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}
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}
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/**
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* dce_mailbox_wait_boot_interface - Waits for mailbox messages.
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*
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* @d : Pointer to tegra_dce
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*
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* Return : 0 if successful
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*/
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static int dce_mailbox_wait_boot_interface(struct tegra_dce *d)
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{
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u32 status;
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enum dce_worker_event_id_type event;
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event = EVENT_ID_DCE_IPC_MESSAGE_SENT;
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dce_worker_thread_wait(d, event);
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status = dce_mailbox_get_interface_status(d,
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DCE_MAILBOX_BOOT_INTERFACE);
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if (dce_worker_get_state(d) == STATE_DCE_WORKER_ABORTED)
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return -EINTR;
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if (status & DCE_BOOT_CMD_ERR_FLAG) {
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dce_parse_boot_status_err(d, status);
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dce_err(d, "Error code received on boot interface : 0x%x",
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status);
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return -EBADE;
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}
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return 0;
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}
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/**
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* dce_boot_interface_init - Initializes the dce boot interface
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* and the associated resources.
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*
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* @d : Pointer to tegra_dce struct
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*
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* Return : 0 if successful
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*/
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int dce_boot_interface_init(struct tegra_dce *d)
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{
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int ret = 0;
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u8 mailbox_id = DCE_MAILBOX_BOOT_INTERFACE;
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ret = dce_mailbox_init_interface(d, mailbox_id,
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DCE_MBOX_BOOT_CMD, DCE_MBOX_IRQ,
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dce_mailbox_wait_boot_interface,
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NULL, dce_boot_interface_isr);
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if (ret) {
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dce_err(d, "Boot Mailbox Interface Init Failed");
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goto err_init;
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}
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err_init:
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return ret;
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}
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/**
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* dce_boot_interface_deinit - Releases the resources
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* associated with dce boot.
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*
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* @d : Pointer to tegra_dce struct.
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*
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* Return : Void
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*/
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void dce_boot_interface_deinit(struct tegra_dce *d)
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{
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dce_mailbox_deinit_interface(d,
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DCE_MAILBOX_BOOT_INTERFACE);
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}
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/**
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* dce_send_version_cmd - Sends the "VERSION" command to dce fw
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*
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* @d : Pointer to tegra_dce struct
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*
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* Return : 0 if successful
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*/
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static int dce_send_version_cmd(struct tegra_dce *d)
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{
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u32 val;
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int ret = 0;
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val = DCE_BOOT_CMD_SET(0U, DCE_BOOT_CMD_VERSION);
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ret = dce_mailbox_send_cmd_sync(d, val, DCE_MAILBOX_BOOT_INTERFACE);
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return ret;
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}
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/**
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* dce_send_set_sid_cmd - Sends the "SET_SID" command to dce fw
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*
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* @d : Pointer to tegra_dce struct
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*
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* Return : 0 if successful
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*/
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static int dce_send_set_sid_cmd(struct tegra_dce *d)
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{
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u32 val;
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int ret = 0;
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val = DCE_BOOT_CMD_SET(0U, DCE_BOOT_CMD_SET_SID) |
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DCE_BOOT_CMD_PARM_SET(0, dce_get_dce_stream_id(d));
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ret = dce_mailbox_send_cmd_sync(d, val, DCE_MAILBOX_BOOT_INTERFACE);
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return ret;
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}
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/**
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* dce_send_channel_int_cmd - Sends the "CHANNEL_INIT" command to dce fw
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*
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* @d : Pointer to tegra_dce struct
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*
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* Return : 0 if successful
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*/
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static int dce_send_channel_int_cmd(struct tegra_dce *d)
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{
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u32 val;
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int ret = 0;
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val = DCE_BOOT_CMD_SET(0U, DCE_BOOT_CMD_CHANNEL_INIT);
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ret = dce_mailbox_send_cmd_sync(d, val, DCE_MAILBOX_BOOT_INTERFACE);
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return ret;
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}
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/**
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* dce_send_set_addr_read_cmd_hi - Sends addr_hi cmd to dce fw.
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*
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* @d : Pointer to tegra_dce struct.
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* @addr : IOVA addr to be sent.
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* @rd_wr : Tells if the addr to be sent is for read or write
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* interface.
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*
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* Return : 0 if successful
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*/
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static int dce_send_set_addr_cmd_hi(struct tegra_dce *d, u32 addr, u8 rd_wr)
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{
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u32 val;
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int ret = 0;
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val = DCE_BOOT_CMD_SET_HILO(0U, 1U) |
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DCE_BOOT_CMD_SET_RDWR(0U, rd_wr) |
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DCE_BOOT_CMD_SET(0U, DCE_BOOT_CMD_SET_ADDR) |
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DCE_BOOT_CMD_PARM_SET(0U, addr);
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ret = dce_mailbox_send_cmd_sync(d, val, DCE_MAILBOX_BOOT_INTERFACE);
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return ret;
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}
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/**
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* dce_send_set_addr_read_cmd_lo - Sends addr_lo cmd to dce fw.
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*
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* @d : Pointer to tegra_dce struct.
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* @addr : IOVA addr to be sent.
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* @rd_wr : Tells if the addr to be sent is for read or write
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* interface.
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*
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* Return : 0 if successful
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*/
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static int dce_send_set_addr_cmd_lo(struct tegra_dce *d, u32 addr, u8 rd_wr)
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{
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u32 val;
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int ret = 0;
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val = DCE_BOOT_CMD_SET_HILO(0U, 0U) |
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DCE_BOOT_CMD_SET_RDWR(0U, rd_wr) |
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DCE_BOOT_CMD_SET(0U, DCE_BOOT_CMD_SET_ADDR) |
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DCE_BOOT_CMD_PARM_SET(0U, addr);
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ret = dce_mailbox_send_cmd_sync(d, val, DCE_MAILBOX_BOOT_INTERFACE);
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return ret;
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}
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/**
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* dce_send_set_addr_read_cmd - Sends the addresses for admin
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* read interface to dce fw.
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*
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* @d : Pointer to tegra_dce struct
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* @rd_buff : Read address
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*
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* Return : 0 if successful
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*/
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static int dce_send_set_addr_read_cmd(struct tegra_dce *d, const u64 rd_buff)
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{
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int ret = 0;
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#define DCE_DATA_NBITS_SHIFT 20
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ret = dce_send_set_addr_cmd_hi(d, rd_buff >> DCE_DATA_NBITS_SHIFT, 0);
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if (ret) {
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dce_err(d, "Sending of SEND_ADDR for READ IOVA HI failed");
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goto err_sending;
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}
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ret = dce_send_set_addr_cmd_lo(d, rd_buff, 0);
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if (ret) {
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dce_err(d, "Sending of SEND_ADDR for READ IOVA LO failed");
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goto err_sending;
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}
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#undef DCE_DATA_NBITS_SHIFT
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err_sending:
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return ret;
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}
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|
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/**
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* dce_send_set_addr_write_cmd - Sends the addresses for admin
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* write interface to dce fw.
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*
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* @d : Pointer to tegra_dce struct
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* @wr_buff : Write address
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*
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* Return : 0 if successful
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*/
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static int dce_send_set_addr_write_cmd(struct tegra_dce *d, const u64 wr_buff)
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{
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int ret = 0;
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#define DCE_DATA_NBITS_SHIFT 20
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ret = dce_send_set_addr_cmd_hi(d, wr_buff >> DCE_DATA_NBITS_SHIFT, 1);
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if (ret) {
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dce_err(d, "Sending of SEND_ADDR for READ IOVA HI failed");
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goto err_sending;
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}
|
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|
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ret = dce_send_set_addr_cmd_lo(d, wr_buff, 1);
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if (ret) {
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dce_err(d, "Sending of SEND_ADDR for READ IOVA LO failed");
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goto err_sending;
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}
|
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#undef DCE_DATA_NBITS_SHIFT
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|
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err_sending:
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return ret;
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}
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|
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/**
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* dce_send_get_fsize_cmd - Sends the "GET_FSIZE" command to dce fw
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*
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* @d : Pointer to tegra_dce struct
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*
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* Return : 0 if successful
|
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*/
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static int dce_send_get_fsize_cmd(struct tegra_dce *d)
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{
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u32 val;
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int ret = 0;
|
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|
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val = DCE_BOOT_CMD_SET(0U, DCE_BOOT_CMD_GET_FSIZE);
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|
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ret = dce_mailbox_send_cmd_sync(d, val, DCE_MAILBOX_BOOT_INTERFACE);
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|
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return ret;
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}
|
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|
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/**
|
|
* dce_send_set_nframes_cmd - Sends the "SET_NFRAMES" command to dce fw.
|
|
*
|
|
* @d : Pointer to tegra_dce struct
|
|
* @nframes : No. of frames
|
|
*
|
|
* Return : 0 if successful
|
|
*/
|
|
static int dce_send_set_nframes_cmd(struct tegra_dce *d, const u8 nframes)
|
|
{
|
|
u32 val;
|
|
int ret = 0;
|
|
|
|
val = DCE_BOOT_CMD_SET(0U, DCE_BOOT_CMD_SET_NFRAMES)
|
|
| DCE_BOOT_CMD_PARM_SET(0U, nframes);
|
|
|
|
ret = dce_mailbox_send_cmd_sync(d, val, DCE_MAILBOX_BOOT_INTERFACE);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* dce_send_set_frames_cmd - Sends the "SET_NFRAMES" command to dce fw.
|
|
*
|
|
* @d : Pointer to tegra_dce struct
|
|
* @nframes : No. of frames
|
|
*
|
|
* Retrun : 0 if successful
|
|
*/
|
|
static int dce_send_set_fsize_cmd(struct tegra_dce *d, const u32 fsize)
|
|
{
|
|
u32 val;
|
|
int ret = 0;
|
|
|
|
val = DCE_BOOT_CMD_SET(0U, DCE_BOOT_CMD_SET_FSIZE)
|
|
| DCE_BOOT_CMD_PARM_SET(0U, fsize);
|
|
|
|
ret = dce_mailbox_send_cmd_sync(d, val, DCE_MAILBOX_BOOT_INTERFACE);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* dce_send_channel_int_cmd - Sends the "CHANNEL_INIT" command to dce fw
|
|
*
|
|
* @d : Pointer to tegra_dce struct
|
|
*
|
|
* Return : 0 if successful
|
|
*/
|
|
static int dce_send_lock_cmd(struct tegra_dce *d)
|
|
{
|
|
u32 val;
|
|
int ret = 0;
|
|
|
|
val = DCE_BOOT_CMD_SET(0U, DCE_BOOT_CMD_LOCK);
|
|
|
|
ret = dce_mailbox_send_cmd_sync(d, val, DCE_MAILBOX_BOOT_INTERFACE);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* dce_bootstrap_send_ast_iova_info - Sends the iova info for AST
|
|
* channel.
|
|
*
|
|
* @d - Pointer to struct tegra_dce.
|
|
*
|
|
* Return : O if successful
|
|
*/
|
|
static int dce_bootstrap_send_ast_iova_info(struct tegra_dce *d)
|
|
{
|
|
u64 iova;
|
|
u32 size;
|
|
int ret = 0;
|
|
|
|
ret = dce_ipc_get_region_iova_info(d, &iova, &size);
|
|
if (ret) {
|
|
dce_err(d, "Failed to get the iova info needed for ast config");
|
|
goto err_sending;
|
|
}
|
|
|
|
#define DCE_DATA_NBITS_SHIFT 20
|
|
ret = dce_mailbox_send_cmd_sync(d,
|
|
DCE_BOOT_CMD_SET_HILO(0U, 1U) |
|
|
DCE_BOOT_CMD_SET(0U, DCE_BOOT_CMD_SET_AST_LENGTH) |
|
|
DCE_BOOT_CMD_PARM_SET(0U, size >> DCE_DATA_NBITS_SHIFT),
|
|
DCE_MAILBOX_BOOT_INTERFACE);
|
|
if (ret) {
|
|
dce_err(d, "Sending of bootstrap cmd SET_AST_LENGTH(HI) failed");
|
|
goto err_sending;
|
|
}
|
|
|
|
ret = dce_mailbox_send_cmd_sync(d,
|
|
DCE_BOOT_CMD_SET_HILO(0U, 0U) |
|
|
DCE_BOOT_CMD_SET(0U, DCE_BOOT_CMD_SET_AST_LENGTH) |
|
|
DCE_BOOT_CMD_PARM_SET(0U, size),
|
|
DCE_MAILBOX_BOOT_INTERFACE);
|
|
if (ret) {
|
|
dce_err(d, "Sending of bootstrap cmd SET_AST_LENGTH(LO) failed");
|
|
goto err_sending;
|
|
}
|
|
|
|
ret = dce_mailbox_send_cmd_sync(d,
|
|
DCE_BOOT_CMD_SET_HILO(0U, 1U) |
|
|
DCE_BOOT_CMD_SET(0U, DCE_BOOT_CMD_SET_AST_IOVA) |
|
|
DCE_BOOT_CMD_PARM_SET(0U, iova >> DCE_DATA_NBITS_SHIFT),
|
|
DCE_MAILBOX_BOOT_INTERFACE);
|
|
if (ret) {
|
|
dce_err(d, "Sending of bootstrap cmd SET_AST_IOVA(HI) failed");
|
|
goto err_sending;
|
|
}
|
|
#undef DCE_DATA_NBITS_SHIFT
|
|
|
|
ret = dce_mailbox_send_cmd_sync(d,
|
|
DCE_BOOT_CMD_SET_HILO(0U, 0U) |
|
|
DCE_BOOT_CMD_SET(0U, DCE_BOOT_CMD_SET_AST_IOVA) |
|
|
DCE_BOOT_CMD_PARM_SET(0U, iova),
|
|
DCE_MAILBOX_BOOT_INTERFACE);
|
|
if (ret) {
|
|
dce_err(d, "Sending of bootstrap cmd SET_AST_IOVA(LO) failed");
|
|
goto err_sending;
|
|
}
|
|
|
|
err_sending:
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* dce_bootstrap_send_admin_ivc_info - Sends the ivc related info for admin
|
|
* channel.
|
|
*
|
|
* @d - Pointer to struct tegra_dce.
|
|
*
|
|
* Return : O if successful
|
|
*/
|
|
static int dce_bootstrap_send_admin_ivc_info(struct tegra_dce *d)
|
|
{
|
|
int ret = 0;
|
|
u32 val = 0;
|
|
|
|
struct dce_ipc_queue_info q_info;
|
|
|
|
ret = dce_admin_get_ipc_channel_info(d, &q_info);
|
|
if (ret) {
|
|
dce_err(d, "Failed to get the admin ivc channel info");
|
|
goto err_sending;
|
|
}
|
|
|
|
ret = dce_send_set_addr_read_cmd(d, (u64)(q_info.tx_iova));
|
|
if (ret) {
|
|
dce_err(d, "Sending of bootstrap cmd set_addr_read failed");
|
|
goto err_sending;
|
|
}
|
|
|
|
ret = dce_send_set_addr_write_cmd(d, (u64)(q_info.rx_iova));
|
|
if (ret) {
|
|
dce_err(d, "Sending of bootstrap cmd set_addr_write failed");
|
|
goto err_sending;
|
|
}
|
|
|
|
ret = dce_send_get_fsize_cmd(d);
|
|
if (ret) {
|
|
dce_err(d, "Sending of bootstrap cmd get_fsize failed");
|
|
goto err_sending;
|
|
}
|
|
|
|
/**
|
|
* It's assummed here that no other command is sent in between.
|
|
*/
|
|
val = dce_mailbox_get_interface_status(d,
|
|
DCE_MAILBOX_BOOT_INTERFACE);
|
|
|
|
ret = dce_send_set_nframes_cmd(d, q_info.nframes);
|
|
if (ret) {
|
|
dce_err(d, "Sending of bootstrap cmd set_nframes failed");
|
|
goto err_sending;
|
|
}
|
|
|
|
ret = dce_send_set_fsize_cmd(d, q_info.frame_sz);
|
|
if (ret) {
|
|
dce_err(d, "Sending of bootstrap cmd set_fsize failed");
|
|
goto err_sending;
|
|
}
|
|
|
|
err_sending:
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* dce_start_bootstrap_flow - Starts sending the boostrap cmds to
|
|
* dce fw in the required sequence.
|
|
*
|
|
* @d : Pointer to tegra_dce struct
|
|
*
|
|
* Return : 0 if successful
|
|
*/
|
|
int dce_start_bootstrap_flow(struct tegra_dce *d)
|
|
{
|
|
u32 val;
|
|
int ret = 0;
|
|
|
|
d->boot_status |= DCE_FW_BOOTSTRAP_START;
|
|
ret = dce_send_version_cmd(d);
|
|
if (ret) {
|
|
dce_err(d, "Sending of bootstrap cmd VERSION failed");
|
|
goto err_sending;
|
|
}
|
|
/**
|
|
* It's assummed here that no other command is sent in between.
|
|
*/
|
|
val = dce_mailbox_get_interface_status(d,
|
|
DCE_MAILBOX_BOOT_INTERFACE);
|
|
|
|
ret = dce_send_set_sid_cmd(d);
|
|
if (ret) {
|
|
dce_err(d, "Sending of bootstrap cmd set_sid failed");
|
|
goto err_sending;
|
|
}
|
|
|
|
ret = dce_bootstrap_send_ast_iova_info(d);
|
|
if (ret) {
|
|
dce_err(d, "Sending of iova info failed");
|
|
goto err_sending;
|
|
}
|
|
|
|
ret = dce_bootstrap_send_admin_ivc_info(d);
|
|
if (ret) {
|
|
dce_err(d, "Sending of ivc channel info failedbootstrap cmd set_sid failed");
|
|
goto err_sending;
|
|
}
|
|
|
|
ret = dce_send_channel_int_cmd(d);
|
|
if (ret) {
|
|
dce_err(d, "Sending of bootstrap cmd channel_int failed");
|
|
goto err_sending;
|
|
}
|
|
|
|
ret = dce_send_lock_cmd(d);
|
|
if (ret) {
|
|
dce_err(d, "Sending of bootstrap cmd lock failed");
|
|
goto err_sending;
|
|
}
|
|
|
|
d->boot_status |= DCE_FW_BOOTSTRAP_DONE;
|
|
return 0;
|
|
|
|
err_sending:
|
|
dce_err(d, "Bootstrap process failed");
|
|
d->boot_status |= DCE_FW_BOOTSTRAP_FAILED;
|
|
return ret;
|
|
}
|