mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
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cdef2b63f6
Drivers in the NVIDIA OOT repository are public and so remove the directories named 'private' to avoid any confusion once these sources are released. Bug 5054840 Change-Id: I9156e3b08df9ce3d90dc0a2b5e72416f28fac5f5 Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3351272 GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Ashish Mhetre <amhetre@nvidia.com> Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
151 lines
3.5 KiB
C
151 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION. All rights reserved.
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#define pr_fmt(fmt) "smmu-hwpm: " fmt
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#include <nvidia/conftest.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/export.h>
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#include <linux/of_device.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <uapi/linux/tegra-soc-hwpm-uapi.h>
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#define SMMU_TCU_PERFMUX_0_OFFSET 0x5000
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static struct tegra_soc_hwpm_ip_ops hwpm_ip_ops;
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struct smmu_hwpm {
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struct device *dev;
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void __iomem *base;
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};
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static u32 smmu_readl(struct smmu_hwpm *smmu, u32 reg)
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{
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return readl(smmu->base + reg);
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}
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static void smmu_writel(struct smmu_hwpm *smmu, u32 val, u32 reg)
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{
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writel(val, smmu->base + reg);
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}
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static int smmu_hwpm_reg_op(void *ip_dev,
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enum tegra_soc_hwpm_ip_reg_op reg_op,
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u32 inst_element_index, u64 reg_offset, u32 *reg_data)
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{
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struct device *dev = (struct device *)ip_dev;
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struct smmu_hwpm *smmu;
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smmu = dev_get_drvdata(dev);
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if (!smmu) {
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pr_err("Invalid device\n");
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return -ENODEV;
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}
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if ((u32)reg_offset != SMMU_TCU_PERFMUX_0_OFFSET) {
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dev_err(smmu->dev, "SOC-HWPM requesting access to prohibited register");
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return -EPERM;
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}
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if (reg_op == TEGRA_SOC_HWPM_IP_REG_OP_READ) {
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*reg_data = smmu_readl(smmu, (u32)reg_offset);
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} else if (reg_op == TEGRA_SOC_HWPM_IP_REG_OP_WRITE) {
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smmu_writel(smmu, *reg_data, (u32)reg_offset);
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} else {
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dev_err(smmu->dev, "Invalid operation\n");
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return -EINVAL;
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}
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return 0;
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}
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static const struct of_device_id smmu_hwpm_of_ids[] = {
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{ .compatible = "nvidia,t264-smmu-hwpm" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, smmu_hwpm_of_ids);
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static int smmu_hwpm_probe(struct platform_device *pdev)
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{
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struct smmu_hwpm *smmu;
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struct resource *res;
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u64 base_addr;
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smmu = devm_kzalloc(&pdev->dev, sizeof(*smmu), GFP_KERNEL);
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if (!smmu)
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return -ENOMEM;
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platform_set_drvdata(pdev, smmu);
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smmu->dev = &pdev->dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(smmu->dev, "Missing SMMU aperture in DT\n");
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return -ENODEV;
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}
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smmu->base = devm_ioremap(smmu->dev, res->start, resource_size(res));
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if (IS_ERR_OR_NULL(smmu->base))
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return PTR_ERR(smmu->base);
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base_addr = res->start;
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hwpm_ip_ops.ip_dev = (void *)smmu->dev;
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hwpm_ip_ops.resource_enum = TEGRA_SOC_HWPM_RESOURCE_SMMU;
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hwpm_ip_ops.ip_base_address = base_addr;
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hwpm_ip_ops.hwpm_ip_reg_op = &smmu_hwpm_reg_op;
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tegra_soc_hwpm_ip_register(&hwpm_ip_ops);
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return 0;
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}
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static void smmu_hwpm_remove(struct platform_device *pdev)
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{
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tegra_soc_hwpm_ip_unregister(&hwpm_ip_ops);
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}
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#if defined(NV_PLATFORM_DRIVER_STRUCT_REMOVE_RETURNS_VOID) /* Linux v6.11 */
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static void smmu_hwpm_remove_wrapper(struct platform_device *pdev)
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{
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smmu_hwpm_remove(pdev);
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}
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#else
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static int smmu_hwpm_remove_wrapper(struct platform_device *pdev)
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{
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smmu_hwpm_remove(pdev);
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return 0;
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}
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#endif
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static struct platform_driver smmu_hwpm_driver = {
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.driver = {
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.name = "tegra264-smmu-hwpm",
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.of_match_table = smmu_hwpm_of_ids,
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.owner = THIS_MODULE,
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},
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.probe = smmu_hwpm_probe,
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.remove = smmu_hwpm_remove_wrapper,
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};
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static int __init smmu_hwpm_init(void)
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{
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return platform_driver_register(&smmu_hwpm_driver);
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}
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module_init(smmu_hwpm_init);
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static void __exit smmu_hwpm_exit(void)
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{
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platform_driver_unregister(&smmu_hwpm_driver);
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}
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module_exit(smmu_hwpm_exit);
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MODULE_AUTHOR("Ashish Mhetre <amhetre@nvidia.com>");
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MODULE_DESCRIPTION("Tegra264 SMMU-HWPM driver");
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MODULE_LICENSE("GPL v2");
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