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dc5237350d
Fix the errors generated when running the dt_binding_check on the DT binding document yaml format. Change-Id: Ie000447c97e92532755a484be02c5b347216d774 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2702785 GVS: Gerrit_Virtual_Submit
66 lines
1.5 KiB
YAML
66 lines
1.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mfd/nvidia-vrs-pseq.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA VRS sequencer driver
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maintainers:
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- Shubhi Garg <shgarg@nvidia.com>
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- Laxman Dewangan <ldewangan@nvidia.com>
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description: |
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NVIDIA VRS sequencer device for controlling the voltage rails.
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properties:
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compatible:
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const: "nvidia,vrs-pseq"
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reg:
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description:
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I2C device address.
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maxItems: 1
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interrupts:
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maxItems: 1
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interrupt-controller: true
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"#interrupt-cells":
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const: 3
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description:
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The first cell is the IRQ number, the second cell is the trigger type.
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-controller
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- "#interrupt-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#define TEGRA234_IRQ_PMIC_EXT_INTR 209
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bpmp {
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i2c {
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#address-cells = <1>;
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#size-cells = <0>;
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vrs@3c {
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compatible = "nvidia,vrs-pseq";
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reg = <0x3c>;
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interrupt-parent = <&intc>;
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/* IRQ is active-low but pmc inverts the signal */
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interrupts = <GIC_SPI TEGRA234_IRQ_PMIC_EXT_INTR IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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};
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};
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