/*
* Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
*
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
*/

#ifndef NVGPU_BOARDOBJGRP_CLASSES_H
#define NVGPU_BOARDOBJGRP_CLASSES_H

/* Enumeration of BOARDOBJGRP class IDs. Used as "classId" argument for
 * communications between Kernel and PMU via the various generic
 * BOARDOBJGRP interfaces.
*/

/* Clk unit */
#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID__FIRST			0x01U
#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_DOMAIN		\
			(NV_PMU_CLK_BOARDOBJGRP_CLASS_ID__FIRST + 0x00U)
#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_PROG		\
			(NV_PMU_CLK_BOARDOBJGRP_CLASS_ID__FIRST + 0x01U)
#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_VIN_DEVICE		\
			(NV_PMU_CLK_BOARDOBJGRP_CLASS_ID__FIRST + 0x02U)
#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_FLL_DEVICE		\
			(NV_PMU_CLK_BOARDOBJGRP_CLASS_ID__FIRST + 0x03U)
#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_VF_POINT		\
			(NV_PMU_CLK_BOARDOBJGRP_CLASS_ID__FIRST + 0x04U)
#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_FREQ_CONTROLLER	\
			(NV_PMU_CLK_BOARDOBJGRP_CLASS_ID__FIRST + 0x05U)
#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_FREQ_DOMAIN		\
			(NV_PMU_CLK_BOARDOBJGRP_CLASS_ID__FIRST + 0x07U)
#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID__LAST			\
			(NV_PMU_CLK_BOARDOBJGRP_CLASS_ID__FIRST + 0x0BU)

/* Volt unit */
#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID__FIRST			\
			(NV_PMU_CLK_BOARDOBJGRP_CLASS_ID__LAST + 0x01U)
#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_RAIL		\
			(NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID__FIRST + 0x00U)
#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_DEVICE		\
			(NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID__FIRST + 0x01U)
#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_POLICY		\
			(NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID__FIRST + 0x02U)
#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID__LAST			\
			(NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID__FIRST + 0x04U)

/* Perf unit */
#define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID__FIRST			\
			(NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID__LAST + 0x01U)
#define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_VAR		\
			(NV_PMU_PERF_BOARDOBJGRP_CLASS_ID__FIRST + 0x00U)
#define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_EQU		\
			(NV_PMU_PERF_BOARDOBJGRP_CLASS_ID__FIRST + 0x01U)
#define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_PSTATE			\
			(NV_PMU_PERF_BOARDOBJGRP_CLASS_ID__FIRST + 0x03U)
#define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID__LAST			\
			(NV_PMU_PERF_BOARDOBJGRP_CLASS_ID__FIRST + 0x05U)

/* Therm unit */
#define NV_PMU_THERM_BOARDOBJGRP_CLASS_ID__FIRST		\
			(NV_PMU_PERF_BOARDOBJGRP_CLASS_ID__LAST + 0x01U)
#define NV_PMU_THERM_BOARDOBJGRP_CLASS_ID_THERM_DEVICE		\
			(NV_PMU_THERM_BOARDOBJGRP_CLASS_ID__FIRST + 0x00U)
#define NV_PMU_THERM_BOARDOBJGRP_CLASS_ID_THERM_CHANNEL		\
			(NV_PMU_THERM_BOARDOBJGRP_CLASS_ID__FIRST + 0x01U)
#define NV_PMU_THERM_BOARDOBJGRP_CLASS_ID__LAST			\
			(NV_PMU_THERM_BOARDOBJGRP_CLASS_ID__FIRST + 0x03U)

#endif /* NVGPU_BOARDOBJGRP_CLASSES_H */
