nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-22 09:12:24 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: update tpc-pg support

Browse Source 
- Add tpc count variable in the platform struct
  to store the number of tpcs present in the  chip.
  This count is needed before GPU boots to provide
  support for static TPC-PG feature.
- Remove valid_tpc_pg_mask and valid_gpc_fbp_pg_mask
  variable from gk20a struct as it is already taken care
  in platform struct.

JIRA NVGPU-8210

Change-Id: Ic04af4b7c24f5e790c52708c117e45a3bb0d1810
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2725960
(cherry picked from commit e9cfae46eb7788e6d12ccd9354ecc46753aba5ce)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2728941
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Divya
2022-06-07 08:21:07 +00:00
committed by mobile promotions
parent 1116d90d32
commit 001e9a2695
4 changed files with 4 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -787,15 +787,6 @@ struct gk20a {
bool can_tpc_pg;
bool can_fbp_pg;
bool can_gpc_pg;
/*
* Valid config array for tpc pg mask
* and gpc/fbp mask. These valid values
* are chip specific and calculated based
* on available number of GPC, FBP and TPC
*/
u32 valid_tpc_pg_mask[MAX_PG_TPC_CONFIGS];
u32 valid_gpc_fbp_pg_mask[MAX_PG_GPC_FBP_CONFIGS];
#endif
#ifdef CONFIG_NVGPU_DGPU

7
drivers/gpu/nvgpu/os/linux/driver_common.c
View File

@@ -182,7 +182,6 @@ static void nvgpu_init_timeslice(struct gk20a *g)
static void nvgpu_init_pm_vars(struct gk20a *g)
{
struct gk20a_platform *platform = dev_get_drvdata(dev_from_gk20a(g));
u32 i = 0;
/*
* Set up initial power settings. For non-slicon platforms, disable
@@ -235,12 +234,6 @@ static void nvgpu_init_pm_vars(struct gk20a *g)
g->can_tpc_pg = platform->can_tpc_pg;
g->can_gpc_pg = platform->can_gpc_pg;
g->can_fbp_pg = platform->can_fbp_pg;
for (i = 0; i < MAX_PG_TPC_CONFIGS; i++)
g->valid_tpc_pg_mask[i] = platform->valid_tpc_pg_mask[i];
for (i = 0; i < MAX_PG_GPC_FBP_CONFIGS; i++)
g->valid_gpc_fbp_pg_mask[i] = platform->valid_gpc_fbp_pg_mask[i];
#endif
g->ldiv_slowdown_factor = platform->ldiv_slowdown_factor_init;
/* if default delay is not set, set default delay to 500msec */

3
drivers/gpu/nvgpu/os/linux/platform_gk20a.h
View File

@@ -126,6 +126,9 @@ struct gk20a_platform {
/* Valid GPC-PG and FBP-PG mask */
u32 valid_gpc_fbp_pg_mask[MAX_PG_GPC_FBP_CONFIGS];
/* available TPC count in a chip */
u32 tpc_count;
#endif
/* Delay before rail gated */
int railgate_delay_init;

2
drivers/gpu/nvgpu/os/linux/sysfs.c
View File

@@ -1123,7 +1123,7 @@ static ssize_t tpc_pg_mask_store(struct device *dev,
!= 0) {
nvgpu_err(g, "golden image size already initialized");
nvgpu_mutex_release(&g->static_pg_lock);
return -ENODEV;
return -EINVAL;
}
if (platform->set_tpc_pg_mask != NULL) {