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gpu: nvgpu: fix MISRA violations in Posix unit

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Fix violations of MISRA rule 5.4 in Posix unit.

JIRA NVGPU-6534

Change-Id: I9471e5fca913ca8cc19403998fdbe5450fb49879
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2488184
(cherry picked from commit f9bc21ca8d96e9c531a1b0077cfe1e78502e7ee5)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2491855
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
ajesh
2021-02-23 11:03:10 +03:00
committed by mobile promotions
parent 1b5a9b28ea
commit 0030dc3eb4
23 changed files with 107 additions and 104 deletions
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10
drivers/gpu/nvgpu/common/engine_queues/engine_mem_queue.c
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -70,7 +70,7 @@ static bool engine_mem_queue_has_room(struct nvgpu_engine_mem_queue *queue,
bool q_rewind = false;
int err = 0;
size = ALIGN(size, QUEUE_ALIGNMENT);
size = NVGPU_ALIGN(size, QUEUE_ALIGNMENT);
err = mem_queue_get_head_tail(queue, &q_head, &q_tail);
if (err != 0) {
@@ -117,7 +117,7 @@ static int engine_mem_queue_rewind(struct nvgpu_falcon *flcn,
goto exit;
} else {
queue->position += nvgpu_safe_cast_u32_to_u8(
ALIGN(U32(cmd.hdr.size), QUEUE_ALIGNMENT));
NVGPU_ALIGN(U32(cmd.hdr.size), QUEUE_ALIGNMENT));
nvgpu_log_info(g, "flcn-%d queue-%d, rewinded",
queue->flcn_id, queue->id);
}
@@ -207,7 +207,7 @@ int nvgpu_engine_mem_queue_push(struct nvgpu_falcon *flcn,
goto unlock_mutex;
}
queue->position += ALIGN(size, QUEUE_ALIGNMENT);
queue->position += NVGPU_ALIGN(size, QUEUE_ALIGNMENT);
err = queue->head(g, queue->id, queue->index,
&queue->position, QUEUE_SET);
@@ -279,7 +279,7 @@ int nvgpu_engine_mem_queue_pop(struct nvgpu_falcon *flcn,
goto unlock_mutex;
}
queue->position += ALIGN(size, QUEUE_ALIGNMENT);
queue->position += NVGPU_ALIGN(size, QUEUE_ALIGNMENT);
err = queue->tail(g, queue->id, queue->index,
&queue->position, QUEUE_SET);