diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ccsr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ccsr_gp10b.h
index e032a70ac..08eccdfb7 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ccsr_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ccsr_gp10b.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_CCSR_GP10B_H
 #define NVGPU_HW_CCSR_GP10B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 ccsr_channel_inst_r(u32 i)
 {
 	return 0x00800000U + i*8U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ce_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ce_gp10b.h
index 3a9256d26..1b6813589 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ce_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ce_gp10b.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_CE_GP10B_H
 #define NVGPU_HW_CE_GP10B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 ce_intr_status_r(u32 i)
 {
 	return 0x00104410U + i*128U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h
index 2f0078fa1..003db2cf7 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_CTXSW_PROG_GP10B_H
 #define NVGPU_HW_CTXSW_PROG_GP10B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 ctxsw_prog_fecs_header_v(void)
 {
 	return 0x00000100U;
@@ -102,7 +104,7 @@ static inline u32 ctxsw_prog_main_image_pm_o(void)
 }
 static inline u32 ctxsw_prog_main_image_pm_mode_m(void)
 {
-	return 0x7U << 0U;
+	return U32(0x7U) << 0U;
 }
 static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
 {
@@ -110,7 +112,7 @@ static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
 }
 static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void)
 {
-	return 0x7U << 3U;
+	return U32(0x7U) << 3U;
 }
 static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void)
 {
@@ -230,7 +232,7 @@ static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v)
 }
 static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void)
 {
-	return 0x3U << 0U;
+	return U32(0x3U) << 0U;
 }
 static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r)
 {
@@ -258,7 +260,7 @@ static inline u32 ctxsw_prog_main_image_misc_options_o(void)
 }
 static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void)
 {
-	return 0x1U << 3U;
+	return U32(0x1U) << 3U;
 }
 static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void)
 {
@@ -318,11 +320,11 @@ static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(void)
 }
 static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m(void)
 {
-	return 0xfffffffU << 0U;
+	return U32(0xfffffffU) << 0U;
 }
 static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m(void)
 {
-	return 0x3U << 28U;
+	return U32(0x3U) << 28U;
 }
 static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f(void)
 {
@@ -398,7 +400,7 @@ static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_f(u32 v)
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_m(void)
 {
-	return 0xffU << 24U;
+	return U32(0xffU) << 24U;
 }
 static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_v(u32 r)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h
index c242fbde4..13a05c416 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_FALCON_GP10B_H
 #define NVGPU_HW_FALCON_GP10B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 falcon_falcon_irqsset_r(void)
 {
 	return 0x00000000U;
@@ -310,7 +312,7 @@ static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v)
 }
 static inline u32 falcon_falcon_cpuctl_halt_intr_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r)
 {
@@ -318,7 +320,7 @@ static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r)
 }
 static inline u32 falcon_falcon_cpuctl_stopped_m(void)
 {
-	return 0x1U << 5U;
+	return U32(0x1U) << 5U;
 }
 static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
 {
@@ -326,7 +328,7 @@ static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
 }
 static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void)
 {
-	return 0x1U << 6U;
+	return U32(0x1U) << 6U;
 }
 static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
 {
@@ -390,11 +392,11 @@ static inline u32 falcon_falcon_dmactl_r(void)
 }
 static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v)
 {
@@ -494,7 +496,7 @@ static inline u32 falcon_falcon_exterrstat_r(void)
 }
 static inline u32 falcon_falcon_exterrstat_valid_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 falcon_falcon_exterrstat_valid_v(u32 r)
 {
@@ -518,7 +520,7 @@ static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v)
 }
 static inline u32 falcon_falcon_icd_cmd_opc_m(void)
 {
-	return 0xfU << 0U;
+	return U32(0xfU) << 0U;
 }
 static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r)
 {
@@ -550,7 +552,7 @@ static inline u32 falcon_falcon_dmemc_offs_f(u32 v)
 }
 static inline u32 falcon_falcon_dmemc_offs_m(void)
 {
-	return 0x3fU << 2U;
+	return U32(0x3fU) << 2U;
 }
 static inline u32 falcon_falcon_dmemc_blk_f(u32 v)
 {
@@ -558,7 +560,7 @@ static inline u32 falcon_falcon_dmemc_blk_f(u32 v)
 }
 static inline u32 falcon_falcon_dmemc_blk_m(void)
 {
-	return 0xffU << 8U;
+	return U32(0xffU) << 8U;
 }
 static inline u32 falcon_falcon_dmemc_aincw_f(u32 v)
 {
@@ -586,7 +588,7 @@ static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v)
 }
 static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void)
 {
-	return 0x1U << 16U;
+	return U32(0x1U) << 16U;
 }
 static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fb_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fb_gp10b.h
index 41c885ac5..79867654e 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fb_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fb_gp10b.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_FB_GP10B_H
 #define NVGPU_HW_FB_GP10B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 fb_fbhub_num_active_ltcs_r(void)
 {
 	return 0x00100800U;
@@ -118,7 +120,7 @@ static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v)
 }
 static inline u32 fb_mmu_invalidate_hubtlb_only_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r)
 {
@@ -138,7 +140,7 @@ static inline u32 fb_mmu_invalidate_replay_f(u32 v)
 }
 static inline u32 fb_mmu_invalidate_replay_m(void)
 {
-	return 0x7U << 3U;
+	return U32(0x7U) << 3U;
 }
 static inline u32 fb_mmu_invalidate_replay_v(u32 r)
 {
@@ -178,7 +180,7 @@ static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v)
 }
 static inline u32 fb_mmu_invalidate_sys_membar_m(void)
 {
-	return 0x1U << 6U;
+	return U32(0x1U) << 6U;
 }
 static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r)
 {
@@ -198,7 +200,7 @@ static inline u32 fb_mmu_invalidate_ack_f(u32 v)
 }
 static inline u32 fb_mmu_invalidate_ack_m(void)
 {
-	return 0x3U << 7U;
+	return U32(0x3U) << 7U;
 }
 static inline u32 fb_mmu_invalidate_ack_v(u32 r)
 {
@@ -226,7 +228,7 @@ static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v)
 }
 static inline u32 fb_mmu_invalidate_cancel_client_id_m(void)
 {
-	return 0x3fU << 9U;
+	return U32(0x3fU) << 9U;
 }
 static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r)
 {
@@ -242,7 +244,7 @@ static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v)
 }
 static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void)
 {
-	return 0x1fU << 15U;
+	return U32(0x1fU) << 15U;
 }
 static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r)
 {
@@ -258,7 +260,7 @@ static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v)
 }
 static inline u32 fb_mmu_invalidate_cancel_client_type_m(void)
 {
-	return 0x1U << 20U;
+	return U32(0x1U) << 20U;
 }
 static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r)
 {
@@ -282,7 +284,7 @@ static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v)
 }
 static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void)
 {
-	return 0x7U << 24U;
+	return U32(0x7U) << 24U;
 }
 static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r)
 {
@@ -330,7 +332,7 @@ static inline u32 fb_mmu_invalidate_trigger_f(u32 v)
 }
 static inline u32 fb_mmu_invalidate_trigger_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 fb_mmu_invalidate_trigger_v(u32 r)
 {
@@ -354,7 +356,7 @@ static inline u32 fb_mmu_debug_wr_aperture_f(u32 v)
 }
 static inline u32 fb_mmu_debug_wr_aperture_m(void)
 {
-	return 0x3U << 0U;
+	return U32(0x3U) << 0U;
 }
 static inline u32 fb_mmu_debug_wr_aperture_v(u32 r)
 {
@@ -430,7 +432,7 @@ static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r)
 }
 static inline u32 fb_mmu_debug_ctrl_debug_m(void)
 {
-	return 0x1U << 16U;
+	return U32(0x1U) << 16U;
 }
 static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h
index 0077f423f..a4df9e5be 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_FIFO_GP10B_H
 #define NVGPU_HW_FIFO_GP10B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 fifo_bar1_base_r(void)
 {
 	return 0x00002254U;
@@ -234,7 +236,7 @@ static inline u32 fifo_intr_en_0_sched_error_f(u32 v)
 }
 static inline u32 fifo_intr_en_0_sched_error_m(void)
 {
-	return 0x1U << 8U;
+	return U32(0x1U) << 8U;
 }
 static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v)
 {
@@ -242,7 +244,7 @@ static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v)
 }
 static inline u32 fifo_intr_en_0_mmu_fault_m(void)
 {
-	return 0x1U << 28U;
+	return U32(0x1U) << 28U;
 }
 static inline u32 fifo_intr_en_1_r(void)
 {
@@ -354,7 +356,7 @@ static inline u32 fifo_fb_timeout_r(void)
 }
 static inline u32 fifo_fb_timeout_period_m(void)
 {
-	return 0x3fffffffU << 0U;
+	return U32(0x3fffffffU) << 0U;
 }
 static inline u32 fifo_fb_timeout_period_max_f(void)
 {
@@ -374,7 +376,7 @@ static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i)
 }
 static inline u32 fifo_sched_disable_runlist_m(u32 i)
 {
-	return 0x1U << (0U + i*1U);
+	return U32(0x1U) << (0U + i*1U);
 }
 static inline u32 fifo_sched_disable_true_v(void)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_flush_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_flush_gp10b.h
index 65e51c9d6..531f28acf 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_flush_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_flush_gp10b.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_FLUSH_GP10B_H
 #define NVGPU_HW_FLUSH_GP10B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 flush_l2_system_invalidate_r(void)
 {
 	return 0x00070004U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h
index 05173bf62..595abb51c 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_FUSE_GP10B_H
 #define NVGPU_HW_FUSE_GP10B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 fuse_status_opt_gpc_r(void)
 {
 	return 0x00021c1cU;
@@ -78,7 +80,7 @@ static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v)
 }
 static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void)
 {
-	return 0xffU << 0U;
+	return U32(0xffU) << 0U;
 }
 static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r)
 {
@@ -94,7 +96,7 @@ static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v)
 }
 static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r)
 {
@@ -118,7 +120,7 @@ static inline u32 fuse_status_opt_fbio_data_f(u32 v)
 }
 static inline u32 fuse_status_opt_fbio_data_m(void)
 {
-	return 0xffffU << 0U;
+	return U32(0xffffU) << 0U;
 }
 static inline u32 fuse_status_opt_fbio_data_v(u32 r)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gmmu_gp10b.h
index 23e0cc495..07fccec03 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gmmu_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gmmu_gp10b.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_GMMU_GP10B_H
 #define NVGPU_HW_GMMU_GP10B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 gmmu_new_pde_is_pte_w(void)
 {
 	return 0U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
index 2cd3750f9..e1e739eaa 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_GR_GP10B_H
 #define NVGPU_HW_GR_GP10B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 gr_intr_r(void)
 {
 	return 0x00400100U;
@@ -166,39 +168,39 @@ static inline u32 gr_exception_r(void)
 }
 static inline u32 gr_exception_fe_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 gr_exception_gpc_m(void)
 {
-	return 0x1U << 24U;
+	return U32(0x1U) << 24U;
 }
 static inline u32 gr_exception_memfmt_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 gr_exception_ds_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 gr_exception_sked_m(void)
 {
-	return 0x1U << 8U;
+	return U32(0x1U) << 8U;
 }
 static inline u32 gr_exception_pd_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 gr_exception_scc_m(void)
 {
-	return 0x1U << 3U;
+	return U32(0x1U) << 3U;
 }
 static inline u32 gr_exception_ssync_m(void)
 {
-	return 0x1U << 5U;
+	return U32(0x1U) << 5U;
 }
 static inline u32 gr_exception_mme_m(void)
 {
-	return 0x1U << 7U;
+	return U32(0x1U) << 7U;
 }
 static inline u32 gr_exception1_r(void)
 {
@@ -218,7 +220,7 @@ static inline u32 gr_exception_en_r(void)
 }
 static inline u32 gr_exception_en_fe_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 gr_exception1_en_r(void)
 {
@@ -394,7 +396,7 @@ static inline u32 gr_activity_4_gpc0_f(u32 v)
 }
 static inline u32 gr_activity_4_gpc0_m(void)
 {
-	return 0x7U << 0U;
+	return U32(0x7U) << 0U;
 }
 static inline u32 gr_activity_4_gpc0_v(u32 r)
 {
@@ -418,7 +420,7 @@ static inline u32 gr_pri_gpcs_gcc_dbg_r(void)
 }
 static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void)
 {
@@ -430,7 +432,7 @@ static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void)
 }
 static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 gr_pri_sked_activity_r(void)
 {
@@ -602,7 +604,7 @@ static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r(void)
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m(void)
 {
-	return 0xffU << 0U;
+	return U32(0xffU) << 0U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(u32 r)
 {
@@ -610,7 +612,7 @@ static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(u32 r
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m(void)
 {
-	return 0xffU << 8U;
+	return U32(0xffU) << 8U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(u32 r)
 {
@@ -618,7 +620,7 @@ static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(u32 r)
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m(void)
 {
-	return 0xffU << 16U;
+	return U32(0xffU) << 16U;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(u32 r)
 {
@@ -646,7 +648,7 @@ static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r(void)
 }
 static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(void)
 {
-	return 0xffffU << 0U;
+	return U32(0xffffU) << 0U;
 }
 static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(u32 r)
 {
@@ -654,7 +656,7 @@ static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(u32 r)
 }
 static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(void)
 {
-	return 0xffffU << 16U;
+	return U32(0xffffU) << 16U;
 }
 static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(u32 r)
 {
@@ -666,7 +668,7 @@ static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r(void)
 }
 static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(void)
 {
-	return 0xffffU << 0U;
+	return U32(0xffffU) << 0U;
 }
 static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(u32 r)
 {
@@ -674,7 +676,7 @@ static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(u32 r)
 }
 static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(void)
 {
-	return 0xffffU << 16U;
+	return U32(0xffffU) << 16U;
 }
 static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(u32 r)
 {
@@ -838,11 +840,11 @@ static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v)
 }
 static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 gr_fecs_os_r(void)
 {
@@ -910,7 +912,7 @@ static inline u32 gr_fecs_icd_cmd_opc_f(u32 v)
 }
 static inline u32 gr_fecs_icd_cmd_opc_m(void)
 {
-	return 0xfU << 0U;
+	return U32(0xfU) << 0U;
 }
 static inline u32 gr_fecs_icd_cmd_opc_v(u32 r)
 {
@@ -974,7 +976,7 @@ static inline u32 gr_fecs_dmemc_offs_f(u32 v)
 }
 static inline u32 gr_fecs_dmemc_offs_m(void)
 {
-	return 0x3fU << 2U;
+	return U32(0x3fU) << 2U;
 }
 static inline u32 gr_fecs_dmemc_offs_v(u32 r)
 {
@@ -1066,7 +1068,7 @@ static inline u32 gr_fecs_current_ctx_target_f(u32 v)
 }
 static inline u32 gr_fecs_current_ctx_target_m(void)
 {
-	return 0x3U << 28U;
+	return U32(0x3U) << 28U;
 }
 static inline u32 gr_fecs_current_ctx_target_v(u32 r)
 {
@@ -1094,7 +1096,7 @@ static inline u32 gr_fecs_current_ctx_valid_f(u32 v)
 }
 static inline u32 gr_fecs_current_ctx_valid_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 gr_fecs_current_ctx_valid_v(u32 r)
 {
@@ -1298,7 +1300,7 @@ static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v)
 }
 static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void)
 {
-	return 0x1U << 10U;
+	return U32(0x1U) << 10U;
 }
 static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r)
 {
@@ -1366,7 +1368,7 @@ static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v)
 }
 static inline u32 gr_fecs_fs_num_available_gpcs_m(void)
 {
-	return 0x1fU << 0U;
+	return U32(0x1fU) << 0U;
 }
 static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r)
 {
@@ -1382,7 +1384,7 @@ static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v)
 }
 static inline u32 gr_fecs_fs_num_available_fbps_m(void)
 {
-	return 0x1fU << 16U;
+	return U32(0x1fU) << 16U;
 }
 static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r)
 {
@@ -1410,7 +1412,7 @@ static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v)
 }
 static inline u32 gr_fecs_rc_lanes_num_chains_m(void)
 {
-	return 0x3fU << 0U;
+	return U32(0x3fU) << 0U;
 }
 static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r)
 {
@@ -1430,7 +1432,7 @@ static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v)
 }
 static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void)
 {
-	return 0x1U << 12U;
+	return U32(0x1U) << 12U;
 }
 static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r)
 {
@@ -1454,7 +1456,7 @@ static inline u32 gr_fecs_new_ctx_ptr_f(u32 v)
 }
 static inline u32 gr_fecs_new_ctx_ptr_m(void)
 {
-	return 0xfffffffU << 0U;
+	return U32(0xfffffffU) << 0U;
 }
 static inline u32 gr_fecs_new_ctx_ptr_v(u32 r)
 {
@@ -1470,7 +1472,7 @@ static inline u32 gr_fecs_new_ctx_target_f(u32 v)
 }
 static inline u32 gr_fecs_new_ctx_target_m(void)
 {
-	return 0x3U << 28U;
+	return U32(0x3U) << 28U;
 }
 static inline u32 gr_fecs_new_ctx_target_v(u32 r)
 {
@@ -1498,7 +1500,7 @@ static inline u32 gr_fecs_new_ctx_valid_f(u32 v)
 }
 static inline u32 gr_fecs_new_ctx_valid_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 gr_fecs_new_ctx_valid_v(u32 r)
 {
@@ -1518,7 +1520,7 @@ static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v)
 }
 static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void)
 {
-	return 0xfffffffU << 0U;
+	return U32(0xfffffffU) << 0U;
 }
 static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r)
 {
@@ -1534,7 +1536,7 @@ static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v)
 }
 static inline u32 gr_fecs_arb_ctx_ptr_target_m(void)
 {
-	return 0x3U << 28U;
+	return U32(0x3U) << 28U;
 }
 static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r)
 {
@@ -1566,7 +1568,7 @@ static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v)
 }
 static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void)
 {
-	return 0x1fU << 0U;
+	return U32(0x1fU) << 0U;
 }
 static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r)
 {
@@ -1882,7 +1884,7 @@ static inline u32 gr_ds_zbc_z_val_f(u32 v)
 }
 static inline u32 gr_ds_zbc_z_val_m(void)
 {
-	return 0xffffffffU << 0U;
+	return U32(0xffffffffU) << 0U;
 }
 static inline u32 gr_ds_zbc_z_val_v(u32 r)
 {
@@ -1970,7 +1972,7 @@ static inline u32 gr_ds_hww_esr_reset_f(u32 v)
 }
 static inline u32 gr_ds_hww_esr_reset_m(void)
 {
-	return 0x1U << 30U;
+	return U32(0x1U) << 30U;
 }
 static inline u32 gr_ds_hww_esr_reset_v(u32 r)
 {
@@ -2002,7 +2004,7 @@ static inline u32 gr_ds_hww_esr_2_reset_f(u32 v)
 }
 static inline u32 gr_ds_hww_esr_2_reset_m(void)
 {
-	return 0x1U << 30U;
+	return U32(0x1U) << 30U;
 }
 static inline u32 gr_ds_hww_esr_2_reset_v(u32 r)
 {
@@ -2214,7 +2216,7 @@ static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v)
 }
 static inline u32 gr_scc_pagepool_max_valid_pages_m(void)
 {
-	return 0x3ffU << 10U;
+	return U32(0x3ffU) << 10U;
 }
 static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r)
 {
@@ -2338,7 +2340,7 @@ static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v)
 }
 static inline u32 gr_gpccs_rc_lanes_num_chains_m(void)
 {
-	return 0x3fU << 0U;
+	return U32(0x3fU) << 0U;
 }
 static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r)
 {
@@ -2358,7 +2360,7 @@ static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v)
 }
 static inline u32 gr_gpccs_rc_lane_size_v_m(void)
 {
-	return 0xffffffU << 0U;
+	return U32(0xffffffU) << 0U;
 }
 static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r)
 {
@@ -2486,7 +2488,7 @@ static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void)
 }
 static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void)
 {
@@ -2502,7 +2504,7 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v)
 }
 static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void)
 {
-	return 0x3fffffU << 0U;
+	return U32(0x3fffffU) << 0U;
 }
 static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void)
 {
@@ -2530,7 +2532,7 @@ static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v)
 }
 static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void)
 {
-	return 0xffffU << 0U;
+	return U32(0xffffU) << 0U;
 }
 static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void)
 {
@@ -2578,7 +2580,7 @@ static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v)
 }
 static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void)
 {
-	return 0x1fffffU << 0U;
+	return U32(0x1fffffU) << 0U;
 }
 static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r)
 {
@@ -2598,7 +2600,7 @@ static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v)
 }
 static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r)
 {
@@ -2618,7 +2620,7 @@ static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_f(u32 v)
 }
 static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(u32 v)
 {
@@ -2626,7 +2628,7 @@ static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(u32 v)
 }
 static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 gr_gpccs_falcon_addr_r(void)
 {
@@ -2642,7 +2644,7 @@ static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v)
 }
 static inline u32 gr_gpccs_falcon_addr_lsb_m(void)
 {
-	return 0x3fU << 0U;
+	return U32(0x3fU) << 0U;
 }
 static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r)
 {
@@ -2666,7 +2668,7 @@ static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v)
 }
 static inline u32 gr_gpccs_falcon_addr_msb_m(void)
 {
-	return 0x3fU << 6U;
+	return U32(0x3fU) << 6U;
 }
 static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r)
 {
@@ -2690,7 +2692,7 @@ static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v)
 }
 static inline u32 gr_gpccs_falcon_addr_ext_m(void)
 {
-	return 0xfffU << 0U;
+	return U32(0xfffU) << 0U;
 }
 static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r)
 {
@@ -2714,11 +2716,11 @@ static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v)
 }
 static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 gr_gpccs_imemc_r(u32 i)
 {
@@ -2794,7 +2796,7 @@ static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v)
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void)
 {
-	return 0xffffffffU << 0U;
+	return U32(0xffffffffU) << 0U;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r)
 {
@@ -2822,7 +2824,7 @@ static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v)
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void)
 {
-	return 0x7ffU << 0U;
+	return U32(0x7ffU) << 0U;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r)
 {
@@ -2846,7 +2848,7 @@ static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v)
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r)
 {
@@ -2926,7 +2928,7 @@ static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v)
 }
 static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void)
 {
-	return 0x3fffffU << 0U;
+	return U32(0x3fffffU) << 0U;
 }
 static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i)
 {
@@ -3286,7 +3288,7 @@ static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v)
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void)
 {
-	return 0x7U << 28U;
+	return U32(0x7U) << 28U;
 }
 static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r)
 {
@@ -3622,7 +3624,7 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void)
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r)
 {
@@ -3658,7 +3660,7 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void)
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r)
 {
@@ -3670,7 +3672,7 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void)
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r)
 {
@@ -3850,11 +3852,11 @@ static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void)
 }
 static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m(void)
 {
-	return 0x1U << 24U;
+	return U32(0x1U) << 24U;
 }
 static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(void)
 {
-	return 0x7U << 25U;
+	return U32(0x7U) << 25U;
 }
 static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f(void)
 {
@@ -3874,7 +3876,7 @@ static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void)
 }
 static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v)
 {
@@ -3890,7 +3892,7 @@ static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void)
 }
 static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v)
 {
@@ -4006,11 +4008,11 @@ static inline u32 gr_bes_crop_debug3_r(void)
 }
 static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void)
 {
@@ -4022,7 +4024,7 @@ static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void)
 }
 static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void)
 {
@@ -4038,7 +4040,7 @@ static inline u32 gr_bes_crop_debug4_r(void)
 }
 static inline u32 gr_bes_crop_debug4_clamp_fp_blend_m(void)
 {
-	return 0x1U << 18U;
+	return U32(0x1U) << 18U;
 }
 static inline u32 gr_bes_crop_debug4_clamp_fp_blend_to_inf_f(void)
 {
@@ -4206,39 +4208,39 @@ static inline u32 gr_gpcs_pri_mmu_ctrl_r(void)
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void)
 {
-	return 0x1U << 11U;
+	return U32(0x1U) << 11U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void)
 {
-	return 0x3U << 3U;
+	return U32(0x3U) << 3U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void)
 {
-	return 0x3U << 5U;
+	return U32(0x3U) << 5U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void)
 {
-	return 0x3U << 28U;
+	return U32(0x3U) << 28U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void)
 {
-	return 0x1U << 30U;
+	return U32(0x1U) << 30U;
 }
 static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void)
 {
@@ -4286,7 +4288,7 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void)
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r)
 {
@@ -4302,7 +4304,7 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void)
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void)
 {
-	return 0x1U << 3U;
+	return U32(0x1U) << 3U;
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void)
 {
@@ -4314,7 +4316,7 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void)
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void)
 {
-	return 0x1U << 30U;
+	return U32(0x1U) << 30U;
 }
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r)
 {
@@ -4342,7 +4344,7 @@ static inline u32 gr_debug_2_r(void)
 }
 static inline u32 gr_debug_2_gfxp_wfi_always_injects_wfi_m(void)
 {
-	return 0x1U << 23U;
+	return U32(0x1U) << 23U;
 }
 static inline u32 gr_debug_2_gfxp_wfi_always_injects_wfi_v(u32 r)
 {
@@ -4366,7 +4368,7 @@ static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v)
 }
 static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void)
 {
-	return 0x7U << 8U;
+	return U32(0x7U) << 8U;
 }
 static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void)
 {
@@ -4378,7 +4380,7 @@ static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void)
 }
 static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void)
 {
-	return 0x3U << 11U;
+	return U32(0x3U) << 11U;
 }
 static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void)
 {
@@ -4394,7 +4396,7 @@ static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v)
 }
 static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void)
 {
-	return 0xffU << 0U;
+	return U32(0xffU) << 0U;
 }
 static inline u32 gr_gpc0_prop_debug1_r(void)
 {
@@ -4406,7 +4408,7 @@ static inline u32 gr_gpc0_prop_debug1_czf_bypass_f(u32 v)
 }
 static inline u32 gr_gpc0_prop_debug1_czf_bypass_m(void)
 {
-	return 0x3U << 14U;
+	return U32(0x3U) << 14U;
 }
 static inline u32 gr_gpc0_prop_debug1_czf_bypass_init_v(void)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ltc_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ltc_gp10b.h
index 3897cdb72..39af4cf83 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ltc_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ltc_gp10b.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_LTC_GP10B_H
 #define NVGPU_HW_LTC_GP10B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 ltc_pltcg_base_v(void)
 {
 	return 0x00140000U;
@@ -90,7 +92,7 @@ static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void)
 }
 static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void)
 {
-	return 0x1U << 15U;
+	return U32(0x1U) << 15U;
 }
 static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void)
 {
@@ -246,7 +248,7 @@ static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v)
 }
 static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void)
 {
-	return 0xffffffffU << 0U;
+	return U32(0xffffffffU) << 0U;
 }
 static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r)
 {
@@ -322,11 +324,11 @@ static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void)
 }
 static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void)
 {
-	return 0x1U << 20U;
+	return U32(0x1U) << 20U;
 }
 static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void)
 {
-	return 0x1U << 30U;
+	return U32(0x1U) << 30U;
 }
 static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void)
 {
@@ -346,7 +348,7 @@ static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void)
 }
 static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void)
 {
-	return 0xffU << 0U;
+	return U32(0xffU) << 0U;
 }
 static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r)
 {
@@ -354,7 +356,7 @@ static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r)
 }
 static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void)
 {
-	return 0xffU << 16U;
+	return U32(0xffU) << 16U;
 }
 static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_mc_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_mc_gp10b.h
index b49e0eadc..71f21ecfb 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_mc_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_mc_gp10b.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_MC_GP10B_H
 #define NVGPU_HW_MC_GP10B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 mc_boot_0_r(void)
 {
 	return 0x00000000U;
@@ -146,7 +148,7 @@ static inline u32 mc_enable_pmedia_f(u32 v)
 }
 static inline u32 mc_enable_pmedia_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 mc_enable_pmedia_v(u32 r)
 {
@@ -158,7 +160,7 @@ static inline u32 mc_enable_priv_ring_enabled_f(void)
 }
 static inline u32 mc_enable_ce0_m(void)
 {
-	return 0x1U << 6U;
+	return U32(0x1U) << 6U;
 }
 static inline u32 mc_enable_pfifo_enabled_f(void)
 {
@@ -186,7 +188,7 @@ static inline u32 mc_enable_pfb_enabled_f(void)
 }
 static inline u32 mc_enable_ce2_m(void)
 {
-	return 0x1U << 21U;
+	return U32(0x1U) << 21U;
 }
 static inline u32 mc_enable_ce2_enabled_f(void)
 {
@@ -222,7 +224,7 @@ static inline u32 mc_enable_pb_0_f(u32 v)
 }
 static inline u32 mc_enable_pb_0_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 mc_enable_pb_0_v(u32 r)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pbdma_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pbdma_gp10b.h
index 748ceddda..fd0b2a7ac 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pbdma_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pbdma_gp10b.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_PBDMA_GP10B_H
 #define NVGPU_HW_PBDMA_GP10B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 pbdma_gp_entry1_r(void)
 {
 	return 0x10000004U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_perf_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_perf_gp10b.h
index 49f2e1f50..c23d182e3 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_perf_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_perf_gp10b.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_PERF_GP10B_H
 #define NVGPU_HW_PERF_GP10B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 perf_pmmsys_base_v(void)
 {
 	return 0x001b0000U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pram_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pram_gp10b.h
index 4fe8aa5b3..474e9ccdb 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pram_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pram_gp10b.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_PRAM_GP10B_H
 #define NVGPU_HW_PRAM_GP10B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 pram_data032_r(u32 i)
 {
 	return 0x00700000U + i*4U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h
index e3ab70549..1386ab4c3 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h
@@ -56,13 +56,15 @@
 #ifndef NVGPU_HW_PRI_RINGMASTER_GP10B_H
 #define NVGPU_HW_PRI_RINGMASTER_GP10B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 pri_ringmaster_command_r(void)
 {
 	return 0x0012004cU;
 }
 static inline u32 pri_ringmaster_command_cmd_m(void)
 {
-	return 0x3fU << 0U;
+	return U32(0x3fU) << 0U;
 }
 static inline u32 pri_ringmaster_command_cmd_v(u32 r)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h
index f902009ba..fe1ce2c77 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_PRI_RINGSTATION_GPC_GP10B_H
 #define NVGPU_HW_PRI_RINGSTATION_GPC_GP10B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
 {
 	return 0x00128300U + i*4U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h
index c316d910a..d85ce6d9e 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_PRI_RINGSTATION_SYS_GP10B_H
 #define NVGPU_HW_PRI_RINGSTATION_SYS_GP10B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 pri_ringstation_sys_master_config_r(u32 i)
 {
 	return 0x00122300U + i*4U;
@@ -66,7 +68,7 @@ static inline u32 pri_ringstation_sys_decode_config_r(void)
 }
 static inline u32 pri_ringstation_sys_decode_config_ring_m(void)
 {
-	return 0x7U << 0U;
+	return U32(0x7U) << 0U;
 }
 static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_proj_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_proj_gp10b.h
index 52f8c2cda..6af34b99f 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_proj_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_proj_gp10b.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_PROJ_GP10B_H
 #define NVGPU_HW_PROJ_GP10B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 proj_gpc_base_v(void)
 {
 	return 0x00500000U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h
index 35245aaef..e1527e36a 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_PWR_GP10B_H
 #define NVGPU_HW_PWR_GP10B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 pwr_falcon_irqsset_r(void)
 {
 	return 0x0010a000U;
@@ -302,7 +304,7 @@ static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v)
 }
 static inline u32 pwr_falcon_cpuctl_halt_intr_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r)
 {
@@ -314,7 +316,7 @@ static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
 }
 static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void)
 {
-	return 0x1U << 6U;
+	return U32(0x1U) << 6U;
 }
 static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
 {
@@ -338,7 +340,7 @@ static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v)
 }
 static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void)
 {
-	return 0x1U << 20U;
+	return U32(0x1U) << 20U;
 }
 static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r)
 {
@@ -390,11 +392,11 @@ static inline u32 pwr_falcon_dmactl_r(void)
 }
 static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void)
 {
-	return 0x1U << 1U;
+	return U32(0x1U) << 1U;
 }
 static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 pwr_falcon_hwcfg_r(void)
 {
@@ -454,7 +456,7 @@ static inline u32 pwr_falcon_exterrstat_r(void)
 }
 static inline u32 pwr_falcon_exterrstat_valid_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 pwr_falcon_exterrstat_valid_v(u32 r)
 {
@@ -478,7 +480,7 @@ static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v)
 }
 static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void)
 {
-	return 0xfU << 0U;
+	return U32(0xfU) << 0U;
 }
 static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r)
 {
@@ -510,7 +512,7 @@ static inline u32 pwr_falcon_dmemc_offs_f(u32 v)
 }
 static inline u32 pwr_falcon_dmemc_offs_m(void)
 {
-	return 0x3fU << 2U;
+	return U32(0x3fU) << 2U;
 }
 static inline u32 pwr_falcon_dmemc_blk_f(u32 v)
 {
@@ -518,7 +520,7 @@ static inline u32 pwr_falcon_dmemc_blk_f(u32 v)
 }
 static inline u32 pwr_falcon_dmemc_blk_m(void)
 {
-	return 0xffU << 8U;
+	return U32(0xffU) << 8U;
 }
 static inline u32 pwr_falcon_dmemc_aincw_f(u32 v)
 {
@@ -582,7 +584,7 @@ static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v)
 }
 static inline u32 pwr_pmu_mutex_id_release_value_m(void)
 {
-	return 0xffU << 0U;
+	return U32(0xffU) << 0U;
 }
 static inline u32 pwr_pmu_mutex_id_release_value_init_v(void)
 {
@@ -702,7 +704,7 @@ static inline u32 pwr_pmu_idle_ctrl_r(u32 i)
 }
 static inline u32 pwr_pmu_idle_ctrl_value_m(void)
 {
-	return 0x3U << 0U;
+	return U32(0x3U) << 0U;
 }
 static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void)
 {
@@ -714,7 +716,7 @@ static inline u32 pwr_pmu_idle_ctrl_value_always_f(void)
 }
 static inline u32 pwr_pmu_idle_ctrl_filter_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void)
 {
@@ -814,7 +816,7 @@ static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v)
 }
 static inline u32 pwr_fbif_transcfg_mem_type_m(void)
 {
-	return 0x1U << 2U;
+	return U32(0x1U) << 2U;
 }
 static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ram_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ram_gp10b.h
index c32f4594f..d247bc56c 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ram_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ram_gp10b.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_RAM_GP10B_H
 #define NVGPU_HW_RAM_GP10B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 ram_in_ramfc_s(void)
 {
 	return 4096U;
@@ -98,7 +100,7 @@ static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v)
 }
 static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void)
 {
-	return 0x1U << 4U;
+	return U32(0x1U) << 4U;
 }
 static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void)
 {
@@ -114,7 +116,7 @@ static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v)
 }
 static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void)
 {
-	return 0x1U << 5U;
+	return U32(0x1U) << 5U;
 }
 static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void)
 {
@@ -130,7 +132,7 @@ static inline u32 ram_in_use_ver2_pt_format_f(u32 v)
 }
 static inline u32 ram_in_use_ver2_pt_format_m(void)
 {
-	return 0x1U << 10U;
+	return U32(0x1U) << 10U;
 }
 static inline u32 ram_in_use_ver2_pt_format_w(void)
 {
@@ -150,7 +152,7 @@ static inline u32 ram_in_big_page_size_f(u32 v)
 }
 static inline u32 ram_in_big_page_size_m(void)
 {
-	return 0x1U << 11U;
+	return U32(0x1U) << 11U;
 }
 static inline u32 ram_in_big_page_size_w(void)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_therm_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_therm_gp10b.h
index 801220d3a..3703768d5 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_therm_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_therm_gp10b.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_THERM_GP10B_H
 #define NVGPU_HW_THERM_GP10B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 therm_use_a_r(void)
 {
 	return 0x00020798U;
@@ -194,7 +196,7 @@ static inline u32 therm_gate_ctrl_r(u32 i)
 }
 static inline u32 therm_gate_ctrl_eng_clk_m(void)
 {
-	return 0x3U << 0U;
+	return U32(0x3U) << 0U;
 }
 static inline u32 therm_gate_ctrl_eng_clk_run_f(void)
 {
@@ -210,7 +212,7 @@ static inline u32 therm_gate_ctrl_eng_clk_stop_f(void)
 }
 static inline u32 therm_gate_ctrl_blk_clk_m(void)
 {
-	return 0x3U << 2U;
+	return U32(0x3U) << 2U;
 }
 static inline u32 therm_gate_ctrl_blk_clk_run_f(void)
 {
@@ -222,7 +224,7 @@ static inline u32 therm_gate_ctrl_blk_clk_auto_f(void)
 }
 static inline u32 therm_gate_ctrl_eng_pwr_m(void)
 {
-	return 0x3U << 4U;
+	return U32(0x3U) << 4U;
 }
 static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void)
 {
@@ -242,7 +244,7 @@ static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v)
 }
 static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void)
 {
-	return 0x1fU << 8U;
+	return U32(0x1fU) << 8U;
 }
 static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v)
 {
@@ -250,7 +252,7 @@ static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v)
 }
 static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void)
 {
-	return 0x7U << 13U;
+	return U32(0x7U) << 13U;
 }
 static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v)
 {
@@ -258,7 +260,7 @@ static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v)
 }
 static inline u32 therm_gate_ctrl_eng_delay_before_m(void)
 {
-	return 0xfU << 16U;
+	return U32(0xfU) << 16U;
 }
 static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v)
 {
@@ -266,7 +268,7 @@ static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v)
 }
 static inline u32 therm_gate_ctrl_eng_delay_after_m(void)
 {
-	return 0xfU << 20U;
+	return U32(0xfU) << 20U;
 }
 static inline u32 therm_fecs_idle_filter_r(void)
 {
@@ -274,7 +276,7 @@ static inline u32 therm_fecs_idle_filter_r(void)
 }
 static inline u32 therm_fecs_idle_filter_value_m(void)
 {
-	return 0xffffffffU << 0U;
+	return U32(0xffffffffU) << 0U;
 }
 static inline u32 therm_hubmmu_idle_filter_r(void)
 {
@@ -282,7 +284,7 @@ static inline u32 therm_hubmmu_idle_filter_r(void)
 }
 static inline u32 therm_hubmmu_idle_filter_value_m(void)
 {
-	return 0xffffffffU << 0U;
+	return U32(0xffffffffU) << 0U;
 }
 static inline u32 therm_clk_slowdown_r(u32 i)
 {
@@ -294,7 +296,7 @@ static inline u32 therm_clk_slowdown_idle_factor_f(u32 v)
 }
 static inline u32 therm_clk_slowdown_idle_factor_m(void)
 {
-	return 0x3fU << 16U;
+	return U32(0x3fU) << 16U;
 }
 static inline u32 therm_clk_slowdown_idle_factor_v(u32 r)
 {
@@ -314,7 +316,7 @@ static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v)
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void)
 {
-	return 0x3fU << 0U;
+	return U32(0x3fU) << 0U;
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void)
 {
@@ -338,7 +340,7 @@ static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v)
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void)
 {
-	return 0x3fU << 6U;
+	return U32(0x3fU) << 6U;
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v)
 {
@@ -346,7 +348,7 @@ static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v)
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void)
 {
-	return 0x3fU << 12U;
+	return U32(0x3fU) << 12U;
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v)
 {
@@ -354,7 +356,7 @@ static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v)
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void)
 {
-	return 0x3fU << 18U;
+	return U32(0x3fU) << 18U;
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v)
 {
@@ -362,7 +364,7 @@ static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v)
 }
 static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void)
 {
-	return 0x3fU << 24U;
+	return U32(0x3fU) << 24U;
 }
 static inline u32 therm_grad_stepping0_r(void)
 {
@@ -378,7 +380,7 @@ static inline u32 therm_grad_stepping0_feature_f(u32 v)
 }
 static inline u32 therm_grad_stepping0_feature_m(void)
 {
-	return 0x1U << 0U;
+	return U32(0x1U) << 0U;
 }
 static inline u32 therm_grad_stepping0_feature_v(u32 r)
 {
@@ -406,7 +408,7 @@ static inline u32 therm_clk_timing_grad_slowdown_f(u32 v)
 }
 static inline u32 therm_clk_timing_grad_slowdown_m(void)
 {
-	return 0x1U << 16U;
+	return U32(0x1U) << 16U;
 }
 static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_timer_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_timer_gp10b.h
index 121d5d55a..c7d14082e 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_timer_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_timer_gp10b.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_TIMER_GP10B_H
 #define NVGPU_HW_TIMER_GP10B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 timer_pri_timeout_r(void)
 {
 	return 0x00009080U;
@@ -66,7 +68,7 @@ static inline u32 timer_pri_timeout_period_f(u32 v)
 }
 static inline u32 timer_pri_timeout_period_m(void)
 {
-	return 0xffffffU << 0U;
+	return U32(0xffffffU) << 0U;
 }
 static inline u32 timer_pri_timeout_period_v(u32 r)
 {
@@ -78,7 +80,7 @@ static inline u32 timer_pri_timeout_en_f(u32 v)
 }
 static inline u32 timer_pri_timeout_en_m(void)
 {
-	return 0x1U << 31U;
+	return U32(0x1U) << 31U;
 }
 static inline u32 timer_pri_timeout_en_v(u32 r)
 {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_top_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_top_gp10b.h
index 6fb168de1..c933498af 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_top_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_top_gp10b.h
@@ -56,6 +56,8 @@
 #ifndef NVGPU_HW_TOP_GP10B_H
 #define NVGPU_HW_TOP_GP10B_H
 
+#include <nvgpu/types.h>
+
 static inline u32 top_num_gpcs_r(void)
 {
 	return 0x00022430U;