diff --git a/drivers/gpu/nvgpu/common/regops/regops.c b/drivers/gpu/nvgpu/common/regops/regops.c
index 3e93a161c..5664f7d7a 100644
--- a/drivers/gpu/nvgpu/common/regops/regops.c
+++ b/drivers/gpu/nvgpu/common/regops/regops.c
@@ -1,7 +1,7 @@
 /*
  * Tegra GK20A GPU Debugger Driver Register Ops
  *
- * Copyright (c) 2013-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2013-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -352,7 +352,7 @@ static int validate_reg_op_offset(struct gk20a *g,
 	}
 
 	if (valid && (op->type != REGOP(TYPE_GLOBAL))) {
-		err = gr_gk20a_get_ctx_buffer_offsets(g,
+		err = g->ops.gr.get_ctx_buffer_offsets(g,
 						      op->offset,
 						      1,
 						      &buf_offset_lo,
diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c
index 52296513e..84ecd5e36 100644
--- a/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c
@@ -1,7 +1,7 @@
 /*
  * GK20A Graphics
  *
- * Copyright (c) 2011-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -1554,7 +1554,7 @@ static int gr_exec_ctx_ops(struct nvgpu_channel *ch,
 				continue;
 			}
 
-			err = gr_gk20a_get_ctx_buffer_offsets(g,
+			err = g->ops.gr.get_ctx_buffer_offsets(g,
 						ctx_ops[i].offset,
 						max_offsets,
 						offsets, offset_addrs,
diff --git a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c
index 52b7380cf..e7eedcf9e 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c
@@ -234,6 +234,7 @@ static const struct gpu_ops gm20b_ops = {
 		.split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr,
 		.get_offset_in_gpccs_segment =
 			gr_gk20a_get_offset_in_gpccs_segment,
+		.get_ctx_buffer_offsets = gr_gk20a_get_ctx_buffer_offsets,
 		.set_debug_mode = gm20b_gr_set_debug_mode,
 		.esr_bpt_pending_events = gm20b_gr_esr_bpt_pending_events,
 #endif /* CONFIG_NVGPU_DEBUGGER */
diff --git a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c
index dbeb095ec..5f856fc4b 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c
@@ -287,6 +287,7 @@ static const struct gpu_ops gp10b_ops = {
 		.split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr,
 		.get_offset_in_gpccs_segment =
 			gr_gk20a_get_offset_in_gpccs_segment,
+		.get_ctx_buffer_offsets = gr_gk20a_get_ctx_buffer_offsets,
 		.set_debug_mode = gm20b_gr_set_debug_mode,
 		.esr_bpt_pending_events = gm20b_gr_esr_bpt_pending_events,
 #endif /* CONFIG_NVGPU_DEBUGGER */
diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
index 1691a413a..23ecf547a 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
@@ -359,6 +359,7 @@ NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 8_7))
 		.split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr,
 		.get_offset_in_gpccs_segment =
 			gr_gk20a_get_offset_in_gpccs_segment,
+		.get_ctx_buffer_offsets = gr_gk20a_get_ctx_buffer_offsets,
 		.set_debug_mode = gm20b_gr_set_debug_mode,
 		.set_mmu_debug_mode = gm20b_gr_set_mmu_debug_mode,
 		.esr_bpt_pending_events = gv11b_gr_esr_bpt_pending_events,
diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
index cd7001061..30211bbf2 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
@@ -383,6 +383,7 @@ static const struct gpu_ops tu104_ops = {
 		.split_fbpa_broadcast_addr = gr_gv100_split_fbpa_broadcast_addr,
 		.get_offset_in_gpccs_segment =
 			gr_tu104_get_offset_in_gpccs_segment,
+		.get_ctx_buffer_offsets = gr_gk20a_get_ctx_buffer_offsets,
 		.set_debug_mode = gm20b_gr_set_debug_mode,
 		.esr_bpt_pending_events = gv11b_gr_esr_bpt_pending_events,
 #endif /* CONFIG_NVGPU_DEBUGGER */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_gr.h b/drivers/gpu/nvgpu/include/nvgpu/gops_gr.h
index 3c73a43ea..d21e00752 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gops_gr.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops_gr.h
@@ -1170,6 +1170,12 @@ struct gops_gr {
 					   u32 num_tpcs, u32 num_ppcs,
 					   u32 reg_list_ppc_count,
 					   u32 *__offset_in_segment);
+	int (*get_ctx_buffer_offsets)(struct gk20a *g,
+					u32 addr,
+					u32 max_offsets,
+					u32 *offsets, u32 *offset_addrs,
+					u32 *num_offsets,
+					bool is_quad, u32 quad);
 	void (*set_debug_mode)(struct gk20a *g, bool enable);
 	int (*set_mmu_debug_mode)(struct gk20a *g,
 				  struct nvgpu_channel *ch, bool enable);