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gpu: nvgpu: pmu: pmgr: fix taint parameter
using nvgpu_memcpy() instead of downcasting the parameter to assign. CID 10074974 Change-Id: I5ce333735dca5fc4e34dd42c9fca432223989bf2 Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2744418 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> GVS: Gerrit_Virtual_Submit
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00fd453830
@@ -530,8 +530,8 @@ static int devinit_get_pwr_policy_table(struct gk20a *g,
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int status = 0;
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int status = 0;
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u8 *ptr = NULL;
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u8 *ptr = NULL;
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struct pmu_board_obj *obj_tmp;
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struct pmu_board_obj *obj_tmp;
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struct pwr_policy_3x_header_struct *packed_hdr;
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struct pwr_policy_3x_header_struct packed_hdr = { 0 };
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struct pwr_policy_3x_header_unpacked hdr;
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struct pwr_policy_3x_header_unpacked hdr = { 0 };
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u32 index;
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u32 index;
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u32 obj_index = 0;
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u32 obj_index = 0;
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size_t pwr_policy_size;
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size_t pwr_policy_size;
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@@ -549,41 +549,41 @@ static int devinit_get_pwr_policy_table(struct gk20a *g,
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goto done;
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goto done;
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}
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}
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packed_hdr = (struct pwr_policy_3x_header_struct *)ptr;
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nvgpu_memcpy((u8 *)&packed_hdr, ptr, VBIOS_POWER_POLICY_3X_HEADER_SIZE_25);
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if (packed_hdr->version !=
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if (packed_hdr.version !=
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VBIOS_POWER_POLICY_VERSION_3X) {
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VBIOS_POWER_POLICY_VERSION_3X) {
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status = -EINVAL;
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status = -EINVAL;
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goto done;
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goto done;
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}
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}
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if (packed_hdr->header_size <
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if (packed_hdr.header_size <
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VBIOS_POWER_POLICY_3X_HEADER_SIZE_25) {
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VBIOS_POWER_POLICY_3X_HEADER_SIZE_25) {
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status = -EINVAL;
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status = -EINVAL;
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goto done;
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goto done;
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}
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}
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if (packed_hdr->table_entry_size <
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if (packed_hdr.table_entry_size <
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VBIOS_POWER_POLICY_3X_ENTRY_SIZE_2E) {
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VBIOS_POWER_POLICY_3X_ENTRY_SIZE_2E) {
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status = -EINVAL;
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status = -EINVAL;
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goto done;
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goto done;
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}
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}
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/* unpack power policy table header */
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/* unpack power policy table header */
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devinit_unpack_pwr_policy_header(&hdr, packed_hdr);
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devinit_unpack_pwr_policy_header(&hdr, &packed_hdr);
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ptr += (u32)hdr.header_size;
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ptr += (u32)hdr.header_size;
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for (index = 0; index < hdr.num_table_entries; index++) {
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for (index = 0; index < hdr.num_table_entries; index++) {
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struct pwr_policy_3x_entry_struct *packed_entry;
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struct pwr_policy_3x_entry_struct packed_entry = { 0 };
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struct pwr_policy_3x_entry_unpacked entry;
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struct pwr_policy_3x_entry_unpacked entry;
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u8 class_type;
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u8 class_type;
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packed_entry = (struct pwr_policy_3x_entry_struct *)ptr;
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nvgpu_memcpy((u8 *)&packed_entry, ptr, hdr.table_entry_size);
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class_type = BIOS_GET_FIELD(u8, packed_entry->flags0,
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class_type = BIOS_GET_FIELD(u8, packed_entry.flags0,
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NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS);
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NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS);
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if (class_type != NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_HW_THRESHOLD) {
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if (class_type != NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_HW_THRESHOLD) {
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@@ -592,7 +592,7 @@ static int devinit_get_pwr_policy_table(struct gk20a *g,
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}
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}
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/* unpack power policy table entry */
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/* unpack power policy table entry */
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devinit_unpack_pwr_policy_entry(&entry, packed_entry);
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devinit_unpack_pwr_policy_entry(&entry, &packed_entry);
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ppwrpolicyobjs->version =
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ppwrpolicyobjs->version =
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CTRL_PMGR_PWR_POLICY_TABLE_VERSION_3X;
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CTRL_PMGR_PWR_POLICY_TABLE_VERSION_3X;
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