From 01039aec35a0b38ff39bccd53fdcd79392ec2de3 Mon Sep 17 00:00:00 2001
From: vinodg <vinodg@nvidia.com>
Date: Fri, 6 Dec 2019 11:06:19 -0800
Subject: [PATCH] gpu: nvgpu: disable unused compute sw method for safety

Add missing check with CONFIG_NVGPU_HAL_NON_FUSA in tu10x
code for NVC0C0_SET_SHADER_EXCEPTIONS.

Jira NVGPU-4454

Change-Id: Id8f0560c5061f7c017c84361059007d936dc53b5
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2257034
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
---
 drivers/gpu/nvgpu/hal/gr/intr/gr_intr_tu104.c | 2 ++
 drivers/gpu/nvgpu/hal/init/hal_tu104.c        | 4 ++--
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_tu104.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_tu104.c
index 3f208d627..b77439b3d 100644
--- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_tu104.c
+++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_tu104.c
@@ -69,9 +69,11 @@ int tu104_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
 
 	if (class_num == TURING_COMPUTE_A) {
 		switch (offset << 2) {
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 		case NVC5C0_SET_SHADER_EXCEPTIONS:
 			g->ops.gr.intr.set_shader_exceptions(g, data);
 			break;
+#endif
 		case NVC5C0_SET_SKEDCHECK:
 			gv11b_gr_intr_set_skedcheck(g, data);
 			break;
diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
index 7f0a2ed22..be4aeb43b 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
@@ -661,8 +661,6 @@ static const struct gpu_ops tu104_ops = {
 		.intr = {
 			.handle_fecs_error = gv11b_gr_intr_handle_fecs_error,
 			.handle_sw_method = tu104_gr_intr_handle_sw_method,
-			.set_shader_exceptions =
-					gv11b_gr_intr_set_shader_exceptions,
 			.handle_class_error =
 					gm20b_gr_intr_handle_class_error,
 			.clear_pending_interrupts =
@@ -722,6 +720,8 @@ static const struct gpu_ops tu104_ops = {
 			.get_sm_no_lock_down_hww_global_esr_mask =
 				gv11b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask,
 #ifdef CONFIG_NVGPU_HAL_NON_FUSA
+			.set_shader_exceptions =
+					gv11b_gr_intr_set_shader_exceptions,
 			.tpc_exception_sm_enable =
 				gm20b_gr_intr_tpc_exception_sm_enable,
 #endif