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gpu: nvgpu: add common api to commit gr context

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g->ops.gr.commit_inst() HAL is used to commit gr context to engine
There is nothing h/w specific in HAL implementation anymore and the
sequence can be unified by checking support for subcontext feature

Remove gr_gv11b_commit_inst() and gr_gk20a_commit_inst() and unify
the sequence in nvgpu_gr_obj_ctx_commit_inst() API in common.gr.obj_ctx
unit. Use this API instead of hal.

Channel subcontext is now directly allocated in gk20a_alloc_obj_ctx()

vGPU code will directly call vGPU implementation vgpu_gr_commit_inst()

Delete the hal apis Since they are no longer needed

Jira NVGPU-1887

Change-Id: Iae1f6be4ab52e3e8628f979f477a300e65c92200
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2090497
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2019-04-04 15:06:41 +05:30
committed by mobile promotions
parent 0957229524
commit 010d01105c
16 changed files with 52 additions and 68 deletions
Download Patch File Download Diff File Expand all files Collapse all files

35
drivers/gpu/nvgpu/common/gr/obj_ctx.c
View File

@@ -31,10 +31,32 @@
#include <nvgpu/gr/gr_falcon.h>
#include <nvgpu/gr/fs_state.h>
#include <nvgpu/power_features/cg.h>
#include <nvgpu/channel.h>
#include "obj_ctx_priv.h"
void nvgpu_gr_obj_ctx_commit_inst_gpu_va(struct gk20a *g,
struct nvgpu_mem *inst_block, u64 gpu_va)
{
g->ops.ramin.set_gr_ptr(g, inst_block, gpu_va);
}
void nvgpu_gr_obj_ctx_commit_inst(struct gk20a *g, struct nvgpu_mem *inst_block,
struct nvgpu_gr_ctx *gr_ctx, struct nvgpu_gr_subctx *subctx, u64 gpu_va)
{
struct nvgpu_mem *ctxheader;
nvgpu_log_fn(g, " ");
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS)) {
nvgpu_gr_subctx_load_ctx_header(g, subctx, gr_ctx, gpu_va);
ctxheader = nvgpu_gr_subctx_get_ctx_header(g, subctx);
nvgpu_gr_obj_ctx_commit_inst_gpu_va(g, inst_block,
ctxheader->gpu_va);
} else {
nvgpu_gr_obj_ctx_commit_inst_gpu_va(g, inst_block, gpu_va);
}
}
static int nvgpu_gr_obj_ctx_init_ctxsw_preemption_mode(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx, struct vm_gk20a *vm,
@@ -529,7 +551,6 @@ int nvgpu_gr_obj_ctx_alloc(struct gk20a *g,
struct nvgpu_gr_global_ctx_buffer_desc *global_ctx_buffer,
struct nvgpu_gr_ctx *gr_ctx,
struct nvgpu_gr_subctx *subctx,
struct channel_gk20a *c,
struct vm_gk20a *vm,
struct nvgpu_mem *inst_block,
u32 class_num, u32 flags,
@@ -582,12 +603,8 @@ int nvgpu_gr_obj_ctx_alloc(struct gk20a *g,
}
/* commit gr ctx buffer */
err = g->ops.gr.commit_inst(c, gr_ctx->mem.gpu_va);
if (err != 0) {
nvgpu_err(g,
"fail to commit gr ctx buffer");
goto out;
}
nvgpu_gr_obj_ctx_commit_inst(g, inst_block, gr_ctx, subctx,
gr_ctx->mem.gpu_va);
/* init golden image, ELPG enabled after this is done */
err = nvgpu_gr_obj_ctx_alloc_golden_ctx_image(g, golden_image, gr_ctx,
@@ -607,7 +624,7 @@ int nvgpu_gr_obj_ctx_alloc(struct gk20a *g,
goto out;
}
nvgpu_gr_obj_ctx_update_ctxsw_preemption_mode(g, gr_ctx, c->subctx);
nvgpu_gr_obj_ctx_update_ctxsw_preemption_mode(g, gr_ctx, subctx);
nvgpu_log_fn(g, "done");
return 0;

1
drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -159,7 +159,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.suspend_contexts = vgpu_gr_suspend_contexts,
.resume_contexts = vgpu_gr_resume_contexts,
.get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
.commit_inst = vgpu_gr_commit_inst,
.trigger_suspend = NULL,
.wait_for_pause = gr_gk20a_wait_for_pause,
.resume_from_pause = NULL,

6
drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c
View File

@@ -79,7 +79,7 @@ void vgpu_gr_detect_sm_arch(struct gk20a *g)
priv->constants.sm_arch_warp_count;
}
int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va)
static int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va)
{
struct tegra_vgpu_cmd_msg msg;
struct tegra_vgpu_ch_ctx_params *p = &msg.params.ch_ctx;
@@ -284,7 +284,7 @@ int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags)
}
/* commit gr ctx buffer */
err = g->ops.gr.commit_inst(c, gr_ctx->mem.gpu_va);
err = vgpu_gr_commit_inst(c, gr_ctx->mem.gpu_va);
if (err) {
nvgpu_err(g, "fail to commit gr ctx buffer");
goto out;
@@ -299,7 +299,7 @@ int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags)
}
} else {
/* commit gr ctx buffer */
err = g->ops.gr.commit_inst(c, gr_ctx->mem.gpu_va);
err = vgpu_gr_commit_inst(c, gr_ctx->mem.gpu_va);
if (err) {
nvgpu_err(g, "fail to commit gr ctx buffer");
goto out;

1
drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.h
View File

@@ -77,7 +77,6 @@ int vgpu_gr_suspend_contexts(struct gk20a *g,
int vgpu_gr_resume_contexts(struct gk20a *g,
struct dbg_session_gk20a *dbg_s,
int *ctx_resident_ch_fd);
int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va);
int vgpu_gr_init_sm_id_table(struct nvgpu_gr_config *gr_config);
int vgpu_gr_init_fs_state(struct gk20a *g);
int vgpu_gr_update_pc_sampling(struct channel_gk20a *ch, bool enable);

1
drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -180,7 +180,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.suspend_contexts = vgpu_gr_suspend_contexts,
.resume_contexts = vgpu_gr_resume_contexts,
.get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
.commit_inst = vgpu_gr_commit_inst,
.trigger_suspend = NULL,
.wait_for_pause = gr_gk20a_wait_for_pause,
.resume_from_pause = NULL,

32
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -178,14 +178,6 @@ static void gr_report_ctxsw_error(struct gk20a *g, u32 err_type, u32 chid,
}
}
int gr_gk20a_commit_inst(struct channel_gk20a *c, u64 gpu_va)
{
struct gk20a *g = c->g;
g->ops.ramin.set_gr_ptr(g, &c->inst_block, gpu_va);
return 0;
}
int gr_gk20a_update_smpc_ctxsw_mode(struct gk20a *g,
struct channel_gk20a *c,
bool enable_smpc_ctxsw)
@@ -431,12 +423,22 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags)
gr_ctx = tsg->gr_ctx;
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS)) {
if (c->subctx == NULL) {
c->subctx = nvgpu_gr_subctx_alloc(g, c->vm);
if (c->subctx == NULL) {
err = -ENOMEM;
goto out;
}
}
}
if (!nvgpu_mem_is_valid(&gr_ctx->mem)) {
tsg->vm = c->vm;
nvgpu_vm_get(tsg->vm);
err = nvgpu_gr_obj_ctx_alloc(g, g->gr.golden_image,
g->gr.global_ctx_buffer, gr_ctx, c->subctx, c,
g->gr.global_ctx_buffer, gr_ctx, c->subctx,
tsg->vm, &c->inst_block, class_num, flags,
c->cde, c->vpr);
if (err != 0) {
@@ -450,12 +452,8 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags)
gr_ctx->tsgid = tsg->tsgid;
} else {
/* commit gr ctx buffer */
err = g->ops.gr.commit_inst(c, gr_ctx->mem.gpu_va);
if (err != 0) {
nvgpu_err(g,
"fail to commit gr ctx buffer");
goto out;
}
nvgpu_gr_obj_ctx_commit_inst(g, &c->inst_block, gr_ctx,
c->subctx, gr_ctx->mem.gpu_va);
}
#ifdef CONFIG_GK20A_CTXSW_TRACE
@@ -472,6 +470,10 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags)
nvgpu_log_fn(g, "done");
return 0;
out:
if (c->subctx != NULL) {
nvgpu_gr_subctx_free(g, c->subctx, c->vm);
}
/* 1. gr_ctx, patch_ctx and global ctx buffer mapping
can be reused so no need to release them.
2. golden image init and load is a one time thing so if

2
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
View File

@@ -364,8 +364,6 @@ int gr_gk20a_resume_from_pause(struct gk20a *g);
int gr_gk20a_clear_sm_errors(struct gk20a *g);
u32 gr_gk20a_tpc_enabled_exceptions(struct gk20a *g);
int gr_gk20a_commit_inst(struct channel_gk20a *c, u64 gpu_va);
void gk20a_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc,
u32 *esr_sm_sel);
void gk20a_gr_init_ovr_sm_dsm_perf(void);

1
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -285,7 +285,6 @@ static const struct gpu_ops gm20b_ops = {
.suspend_contexts = gr_gk20a_suspend_contexts,
.resume_contexts = gr_gk20a_resume_contexts,
.get_preemption_mode_flags = gr_gm20b_get_preemption_mode_flags,
.commit_inst = gr_gk20a_commit_inst,
.trigger_suspend = gr_gk20a_trigger_suspend,
.wait_for_pause = gr_gk20a_wait_for_pause,
.resume_from_pause = gr_gk20a_resume_from_pause,

1
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -314,7 +314,6 @@ static const struct gpu_ops gp10b_ops = {
.suspend_contexts = gr_gp10b_suspend_contexts,
.resume_contexts = gr_gk20a_resume_contexts,
.get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
.commit_inst = gr_gk20a_commit_inst,
.trigger_suspend = gr_gk20a_trigger_suspend,
.wait_for_pause = gr_gk20a_wait_for_pause,
.resume_from_pause = gr_gk20a_resume_from_pause,

1
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -427,7 +427,6 @@ static const struct gpu_ops gv100_ops = {
.suspend_contexts = gr_gp10b_suspend_contexts,
.resume_contexts = gr_gk20a_resume_contexts,
.get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
.commit_inst = gr_gv11b_commit_inst,
.trigger_suspend = gv11b_gr_sm_trigger_suspend,
.wait_for_pause = gr_gk20a_wait_for_pause,
.resume_from_pause = gv11b_gr_resume_from_pause,

28
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -1733,34 +1733,6 @@ u32 gr_gv11b_get_nonpes_aware_tpc(struct gk20a *g, u32 gpc, u32 tpc)
return tpc_new;
}
int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va)
{
struct nvgpu_mem *ctxheader;
struct gk20a *g = c->g;
struct tsg_gk20a *tsg;
nvgpu_log_fn(g, " ");
tsg = tsg_gk20a_from_ch(c);
if (tsg == NULL) {
return -EINVAL;
}
if (c->subctx == NULL) {
c->subctx = nvgpu_gr_subctx_alloc(g, c->vm);
if (c->subctx == NULL) {
return -ENOMEM;
}
}
nvgpu_gr_subctx_load_ctx_header(g, c->subctx, tsg->gr_ctx, gpu_va);
ctxheader = nvgpu_gr_subctx_get_ctx_header(g, c->subctx);
g->ops.ramin.set_gr_ptr(g, &c->inst_block, ctxheader->gpu_va);
return 0;
}
void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc,
u32 *esr_sm_sel)
{

1
drivers/gpu/nvgpu/gv11b/gr_gv11b.h
View File

@@ -98,7 +98,6 @@ int gr_gv11b_handle_fecs_error(struct gk20a *g,
struct nvgpu_gr_isr_data *isr_data);
int gr_gv11b_init_sw_veid_bundle(struct gk20a *g);
void gr_gv11b_detect_sm_arch(struct gk20a *g);
int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va);
void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc,
u32 *esr_sm_sel);
int gv11b_gr_sm_trigger_suspend(struct gk20a *g);

1
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -379,7 +379,6 @@ static const struct gpu_ops gv11b_ops = {
.suspend_contexts = gr_gp10b_suspend_contexts,
.resume_contexts = gr_gk20a_resume_contexts,
.get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
.commit_inst = gr_gv11b_commit_inst,
.trigger_suspend = gv11b_gr_sm_trigger_suspend,
.wait_for_pause = gr_gk20a_wait_for_pause,
.resume_from_pause = gv11b_gr_resume_from_pause,

1
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -396,7 +396,6 @@ struct gpu_ops {
u32 compute_preempt_mode);
int (*set_boosted_ctx)(struct channel_gk20a *ch, bool boost);
int (*init_sw_veid_bundle)(struct gk20a *g);
int (*commit_inst)(struct channel_gk20a *c, u64 gpu_va);
int (*trigger_suspend)(struct gk20a *g);
int (*wait_for_pause)(struct gk20a *g, struct nvgpu_warpstate *w_state);
int (*resume_from_pause)(struct gk20a *g);

7
drivers/gpu/nvgpu/include/nvgpu/gr/obj_ctx.h
View File

@@ -35,6 +35,12 @@ struct nvgpu_mem;
struct channel_gk20a;
struct nvgpu_gr_obj_ctx_golden_image;
void nvgpu_gr_obj_ctx_commit_inst_gpu_va(struct gk20a *g,
struct nvgpu_mem *inst_block, u64 gpu_va);
void nvgpu_gr_obj_ctx_commit_inst(struct gk20a *g, struct nvgpu_mem *inst_block,
struct nvgpu_gr_ctx *gr_ctx, struct nvgpu_gr_subctx *subctx,
u64 gpu_va);
int nvgpu_gr_obj_ctx_set_ctxsw_preemption_mode(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx, struct vm_gk20a *vm, u32 class,
u32 graphics_preempt_mode, u32 compute_preempt_mode);
@@ -54,7 +60,6 @@ int nvgpu_gr_obj_ctx_alloc(struct gk20a *g,
struct nvgpu_gr_global_ctx_buffer_desc *global_ctx_buffer,
struct nvgpu_gr_ctx *gr_ctx,
struct nvgpu_gr_subctx *subctx,
struct channel_gk20a *c,
struct vm_gk20a *vm,
struct nvgpu_mem *inst_block,
u32 class_num, u32 flags,

1
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -448,7 +448,6 @@ static const struct gpu_ops tu104_ops = {
.suspend_contexts = gr_gp10b_suspend_contexts,
.resume_contexts = gr_gk20a_resume_contexts,
.get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
.commit_inst = gr_gv11b_commit_inst,
.trigger_suspend = gv11b_gr_sm_trigger_suspend,
.wait_for_pause = gr_gk20a_wait_for_pause,
.resume_from_pause = gv11b_gr_resume_from_pause,