diff --git a/drivers/gpu/nvgpu/common/pmu/pmgr/pmgrpmu.c b/drivers/gpu/nvgpu/common/pmu/pmgr/pmgrpmu.c
index 65c75dd33..dfa9ae1f6 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmgr/pmgrpmu.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmgr/pmgrpmu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -27,6 +27,7 @@
 #include <nvgpu/boardobjgrp.h>
 #include <nvgpu/boardobjgrp_e32.h>
 #include <nvgpu/string.h>
+#include <nvgpu/bug.h>
 
 #include "gp106/bios_gp106.h"
 
@@ -155,15 +156,18 @@ static int pmgr_send_i2c_device_topology_to_pmu(struct gk20a *g)
 	int status = 0;
 
 	/* INA3221 I2C device info */
-	i2c_desc_table.dev_mask = (1UL << idx);
+	i2c_desc_table.dev_mask = BIT32(idx);
 
 	/* INA3221 */
 	i2c_desc_table.devices[idx].super.type = 0x4E;
 
-	i2c_desc_table.devices[idx].dcb_index = idx;
-	i2c_desc_table.devices[idx].i2c_address = g->ina3221_i2c_address;
+	nvgpu_assert(idx < NV_PMU_PMGR_I2C_DEVICE_DESC_TABLE_MAX_DEVICES);
+	i2c_desc_table.devices[idx].dcb_index = (u8)idx;
+	nvgpu_assert(g->ina3221_i2c_address < (u32)U16_MAX);
+	i2c_desc_table.devices[idx].i2c_address = (u16)g->ina3221_i2c_address;
 	i2c_desc_table.devices[idx].i2c_flags = 0xC2F;
-	i2c_desc_table.devices[idx].i2c_port = g->ina3221_i2c_port;
+	nvgpu_assert(g->ina3221_i2c_port <= (u32)U8_MAX);
+	i2c_desc_table.devices[idx].i2c_port = (u8)g->ina3221_i2c_port;
 
 	/* Pass the table down the PMU as an object */
 	status = pmgr_pmu_set_object(
@@ -281,7 +285,7 @@ static int pmgr_send_pwr_mointer_to_pmu(struct gk20a *g)
 	}
 
 	/* Calculate the max Dmem buffer size */
-	max_dmem_size = sizeof(union nv_pmu_pmgr_pwr_monitor_dmem_size);
+	max_dmem_size = (u32)sizeof(union nv_pmu_pmgr_pwr_monitor_dmem_size);
 
 	/* Pass the table down the PMU as an object */
 	status = pmgr_pmu_set_object(
@@ -366,7 +370,7 @@ static int pmgr_send_pwr_policy_to_pmu(struct gk20a *g)
 			&ppwrpack->violations.hdr.data.super,
 			g->pmgr_pmu->pmgr_policyobjs.pwr_violations.super.objmask);
 
-	max_dmem_size = sizeof(union nv_pmu_pmgr_pwr_policy_dmem_size);
+	max_dmem_size = (u32)sizeof(union nv_pmu_pmgr_pwr_policy_dmem_size);
 
 	/* Pass the table down the PMU as an object */
 	status = pmgr_pmu_set_object(
@@ -415,7 +419,7 @@ int pmgr_pmu_pwr_devices_query_blocking(
 	pcmd->dev_mask = pwr_dev_mask;
 
 	payload.out.buf = ppayload;
-	payload.out.size = sizeof(struct nv_pmu_pmgr_pwr_devices_query_payload);
+	payload.out.size = (u32)sizeof(struct nv_pmu_pmgr_pwr_devices_query_payload);
 	payload.out.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
 	payload.out.offset = NV_PMU_PMGR_PWR_DEVICES_QUERY_ALLOC_OFFSET;
 
diff --git a/drivers/gpu/nvgpu/common/pmu/pmgr/pwrmonitor.c b/drivers/gpu/nvgpu/common/pmu/pmgr/pwrmonitor.c
index d463895d7..d6803f5d0 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmgr/pwrmonitor.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmgr/pwrmonitor.c
@@ -81,7 +81,7 @@ static int _pwr_channel_rels_pmudata_instget(struct gk20a *g,
 	return 0;
 }
 
-static u32 _pwr_channel_state_init(struct gk20a *g)
+static int _pwr_channel_state_init(struct gk20a *g)
 {
 	u8 indx = 0;
 	struct pwr_channel *pchannel;
@@ -369,7 +369,8 @@ int pmgr_monitor_sw_setup(struct gk20a *g)
 	BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct pwr_channel *, pchannel, indx) {
 		if (_pwr_channel_implements(pchannel,
 				CTRL_PMGR_PWR_CHANNEL_TYPE_SENSOR)) {
-			g->pmgr_pmu->pmgr_monitorobjs.physical_channel_mask  |= BIT(indx);
+			g->pmgr_pmu->pmgr_monitorobjs.physical_channel_mask  |=
+								BIT32(indx);
 		}
 	}
 
diff --git a/drivers/gpu/nvgpu/common/pmu/pmgr/pwrpolicy.c b/drivers/gpu/nvgpu/common/pmu/pmgr/pwrpolicy.c
index 26284a08e..33ebf7c03 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmgr/pwrpolicy.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmgr/pwrpolicy.c
@@ -668,7 +668,7 @@ static int devinit_get_pwr_policy_table(struct gk20a *g,
 		pwr_policy_data.pwrpolicy.filter_param.iir.divisor = 0;
 
 		hw_threshold_policy_index |=
-			BIT(pwr_policy_data.hw_threshold.threshold_idx);
+			BIT32(pwr_policy_data.hw_threshold.threshold_idx);
 
 		boardobj = construct_pwr_policy(g, &pwr_policy_data,
 				pwr_policy_size, pwr_policy_data.boardobj.type);
@@ -751,7 +751,7 @@ int pmgr_policy_sw_setup(struct gk20a *g)
 	}
 
 	(void) memset(g->pmgr_pmu->pmgr_policyobjs.policy_idxs,
-		CTRL_PMGR_PWR_POLICY_INDEX_INVALID,
+		(int)CTRL_PMGR_PWR_POLICY_INDEX_INVALID,
 		sizeof(u8) * CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES);
 
 	/* Initialize external power limit policy indexes to _INVALID/0xFF */
@@ -761,7 +761,7 @@ int pmgr_policy_sw_setup(struct gk20a *g)
 	}
 
 	/* Initialize external power state to _D1 */
-	g->pmgr_pmu->pmgr_policyobjs.ext_power_state = 0xFFFFFFFF;
+	g->pmgr_pmu->pmgr_policyobjs.ext_power_state = -1;
 
 	ppwrpolicyobjs = &(g->pmgr_pmu->pmgr_policyobjs);
 	pboardobjgrp = &(g->pmgr_pmu->pmgr_policyobjs.pwr_policies.super);