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gpu: nvgpu: vgpu: add num_pce to constants

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Implement hal gops->ce2.get_num_pce.

Jira VFND-3797

Change-Id: Ie4fd3f170f2961ab5ebd1867b83bfda40e57aa2b
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1543020
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Richard Zhao
2017-08-17 10:32:17 -07:00
committed by mobile promotions
parent 0e0767672a
commit 0130c7ba43
4 changed files with 19 additions and 1 deletions
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14
drivers/gpu/nvgpu/vgpu/ce2_vgpu.c
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@@ -1,7 +1,7 @@
/* /*
* Virtualized GPU CE2 * Virtualized GPU CE2
* *
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
@@ -33,3 +33,15 @@ int vgpu_ce2_nonstall_isr(struct gk20a *g,
return 0; return 0;
} }
static u32 vgpu_ce_get_num_pce(struct gk20a *g)
{
struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
return priv->constants.num_pce;
}
void vgpu_init_ce2_ops(struct gpu_ops *gops)
{
gops->ce2.get_num_pce = vgpu_ce_get_num_pce;
}

1
drivers/gpu/nvgpu/vgpu/vgpu.c
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@@ -440,6 +440,7 @@ void vgpu_init_hal_common(struct gk20a *g)
#if defined(CONFIG_GK20A_CYCLE_STATS) #if defined(CONFIG_GK20A_CYCLE_STATS)
vgpu_init_css_ops(gops); vgpu_init_css_ops(gops);
#endif #endif
vgpu_init_ce2_ops(gops);
gops->chip_init_gpu_characteristics = vgpu_init_gpu_characteristics; gops->chip_init_gpu_characteristics = vgpu_init_gpu_characteristics;
gops->bus.read_ptimer = vgpu_read_ptimer; gops->bus.read_ptimer = vgpu_read_ptimer;
gops->bus.get_timestamps_zipper = vgpu_get_timestamps_zipper; gops->bus.get_timestamps_zipper = vgpu_get_timestamps_zipper;

4
drivers/gpu/nvgpu/vgpu/vgpu.h
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@@ -94,6 +94,7 @@ void vgpu_init_tsg_ops(struct gpu_ops *gops);
#if defined(CONFIG_GK20A_CYCLE_STATS) #if defined(CONFIG_GK20A_CYCLE_STATS)
void vgpu_init_css_ops(struct gpu_ops *gops); void vgpu_init_css_ops(struct gpu_ops *gops);
#endif #endif
void vgpu_init_ce2_ops(struct gpu_ops *gops);
int vgpu_init_mm_support(struct gk20a *g); int vgpu_init_mm_support(struct gk20a *g);
int vgpu_init_gr_support(struct gk20a *g); int vgpu_init_gr_support(struct gk20a *g);
int vgpu_init_fifo_support(struct gk20a *g); int vgpu_init_fifo_support(struct gk20a *g);
@@ -178,6 +179,9 @@ static inline void vgpu_init_css_ops(struct gpu_ops *gops)
{ {
} }
#endif #endif
static inline void vgpu_init_ce2_ops(struct gpu_ops *gops)
{
}
static inline int vgpu_init_mm_support(struct gk20a *g) static inline int vgpu_init_mm_support(struct gk20a *g)
{ {
return -ENOSYS; return -ENOSYS;

1
include/linux/tegra_vgpu.h
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@@ -477,6 +477,7 @@ struct tegra_vgpu_constants_params {
u32 preempt_ctx_size; u32 preempt_ctx_size;
u32 channel_base; u32 channel_base;
struct tegra_vgpu_engines_info engines_info; struct tegra_vgpu_engines_info engines_info;
u32 num_pce;
}; };
struct tegra_vgpu_channel_cyclestats_snapshot_params { struct tegra_vgpu_channel_cyclestats_snapshot_params {