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gpu: nvgpu: vgpu: add num_pce to constants
Implement hal gops->ce2.get_num_pce. Jira VFND-3797 Change-Id: Ie4fd3f170f2961ab5ebd1867b83bfda40e57aa2b Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1543020 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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@@ -1,7 +1,7 @@
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/*
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* Virtualized GPU CE2
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*
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* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@@ -33,3 +33,15 @@ int vgpu_ce2_nonstall_isr(struct gk20a *g,
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return 0;
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}
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static u32 vgpu_ce_get_num_pce(struct gk20a *g)
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{
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struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
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return priv->constants.num_pce;
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}
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void vgpu_init_ce2_ops(struct gpu_ops *gops)
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{
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gops->ce2.get_num_pce = vgpu_ce_get_num_pce;
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}
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@@ -440,6 +440,7 @@ void vgpu_init_hal_common(struct gk20a *g)
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#if defined(CONFIG_GK20A_CYCLE_STATS)
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vgpu_init_css_ops(gops);
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#endif
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vgpu_init_ce2_ops(gops);
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gops->chip_init_gpu_characteristics = vgpu_init_gpu_characteristics;
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gops->bus.read_ptimer = vgpu_read_ptimer;
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gops->bus.get_timestamps_zipper = vgpu_get_timestamps_zipper;
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@@ -94,6 +94,7 @@ void vgpu_init_tsg_ops(struct gpu_ops *gops);
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#if defined(CONFIG_GK20A_CYCLE_STATS)
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void vgpu_init_css_ops(struct gpu_ops *gops);
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#endif
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void vgpu_init_ce2_ops(struct gpu_ops *gops);
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int vgpu_init_mm_support(struct gk20a *g);
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int vgpu_init_gr_support(struct gk20a *g);
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int vgpu_init_fifo_support(struct gk20a *g);
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@@ -178,6 +179,9 @@ static inline void vgpu_init_css_ops(struct gpu_ops *gops)
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{
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}
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#endif
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static inline void vgpu_init_ce2_ops(struct gpu_ops *gops)
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{
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}
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static inline int vgpu_init_mm_support(struct gk20a *g)
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{
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return -ENOSYS;
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@@ -477,6 +477,7 @@ struct tegra_vgpu_constants_params {
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u32 preempt_ctx_size;
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u32 channel_base;
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struct tegra_vgpu_engines_info engines_info;
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u32 num_pce;
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};
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struct tegra_vgpu_channel_cyclestats_snapshot_params {
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