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gpu: nvgpu: limit number of gpfifo entries
Limit number of gpfifo entries so that the size of gpfifo i.e. num_entries * size of each entry fits in u32 data type. Jira NVGPU-5846 Change-Id: I4d3560a6ed90044c88ee3a7acd2e6cb0591b7c5e Signed-off-by: shashank singh <shashsingh@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2474118 (cherry picked from commit 02ab9e163f5b413b6eb9817ab8ac5581ce7ef427) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2483947 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: Dinesh T <dt@nvidia.com> Reviewed-by: Ankur Kishore <ankkishore@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
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@@ -1344,11 +1344,43 @@ long gk20a_channel_ioctl(struct file *filp,
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break;
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}
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/*
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* This restriction is because the last entry is kept empty and used to
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* determine buffer empty or full condition. Additionally, kmd submit
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* uses pre/post sync which need another entry.
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*/
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if ((setup_bind_args.flags &
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NVGPU_CHANNEL_SETUP_BIND_FLAGS_USERMODE_SUPPORT) != 0U) {
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if (setup_bind_args.num_gpfifo_entries < 2U) {
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err = -EINVAL;
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gk20a_idle(ch->g);
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break;
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}
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} else {
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if (setup_bind_args.num_gpfifo_entries < 4U) {
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err = -EINVAL;
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gk20a_idle(ch->g);
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break;
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}
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}
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if (!is_power_of_2(setup_bind_args.num_gpfifo_entries)) {
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err = -EINVAL;
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gk20a_idle(ch->g);
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break;
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}
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/*
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* setup_bind_args.num_gpfifo_entries * nvgpu_get_gpfifo_entry_size() has
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* to fit in u32.
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*/
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if (setup_bind_args.num_gpfifo_entries >
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(U32_MAX / nvgpu_get_gpfifo_entry_size())) {
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err = -EINVAL;
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gk20a_idle(ch->g);
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break;
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}
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err = nvgpu_channel_setup_bind(ch, &setup_bind_args);
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channel_setup_bind_args->work_submit_token =
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setup_bind_args.work_submit_token;
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@@ -1371,11 +1403,44 @@ long gk20a_channel_ioctl(struct file *filp,
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break;
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}
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/*
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* This restriction is because the last entry is kept empty and used to
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* determine buffer empty or full condition. Additionally, kmd submit
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* uses pre/post sync which need another entry.
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*/
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if ((alloc_gpfifo_ex_args->flags &
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NVGPU_CHANNEL_SETUP_BIND_FLAGS_USERMODE_SUPPORT) != 0U) {
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if (alloc_gpfifo_ex_args->num_entries < 2U) {
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err = -EINVAL;
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gk20a_idle(ch->g);
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break;
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}
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} else {
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if (alloc_gpfifo_ex_args->num_entries < 4U) {
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err = -EINVAL;
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gk20a_idle(ch->g);
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break;
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}
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}
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if (!is_power_of_2(alloc_gpfifo_ex_args->num_entries)) {
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err = -EINVAL;
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gk20a_idle(ch->g);
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break;
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}
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/*
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* alloc_gpfifo_ex_args->num_entries * nvgpu_get_gpfifo_entry_size() has
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* to fit in u32.
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*/
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if (alloc_gpfifo_ex_args->num_entries >
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(U32_MAX / nvgpu_get_gpfifo_entry_size())) {
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err = -EINVAL;
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gk20a_idle(ch->g);
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break;
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}
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err = nvgpu_channel_setup_bind(ch, &setup_bind_args);
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gk20a_idle(ch->g);
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break;
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