From 019bee2174c831db20f6e6d5446f9ba4c8e99da1 Mon Sep 17 00:00:00 2001 From: Rajesh Devaraj Date: Fri, 20 May 2022 09:51:35 +0000 Subject: [PATCH] gpu: nvgpu: add additional registers to allowlist To add GL/VK support for shader debugging via the SM trap handler functionality, a write operation to the following PRI registers need to be allowed in all chips (ga10b, gv11b, gm20b, gp10b): - NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL - NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED - NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0 - NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK - NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_REPORT_MASK In this patch, we are adding the above registers into allowlist, if they were absent. Note that these registers included only in non-safety using CONFIG_NVGPU_SET_FALCON_ACCESS_MAP flag. Bug 3642131 Change-Id: I5f62731944b6b3e059afa80a491c3cf5c3656f60 Signed-off-by: Rajesh Devaraj Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2715799 Reviewed-by: svcacv Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-cert Reviewed-by: svc-mobile-misra Reviewed-by: Christopher Lentini Reviewed-by: Vaibhav Kachore GVS: Gerrit_Virtual_Submit Tested-by: Christopher Lentini --- drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.c | 3 +++ drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c | 4 ++++ drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c | 3 +++ 3 files changed, 10 insertions(+) diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.c index 464775b75..faaaa12c7 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.c +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.c @@ -88,6 +88,7 @@ void ga10b_gr_init_get_access_map(struct gk20a *g, 0x418380, /* gr_pri_gpcs_rasterarb_line_class */ 0x418800, /* gr_pri_gpcs_setup_debug */ 0x418830, /* gr_pri_gpcs_setup_debug_z_gamut_offset */ + 0x4188b0, /* gr_pri_gpcs_mmu_debug_ctrl */ 0x4188fc, /* gr_pri_gpcs_zcull_ctx_debug */ 0x418e00, /* gr_pri_gpcs_swdx_config */ 0x418e40, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */ @@ -114,9 +115,11 @@ void ga10b_gr_init_get_access_map(struct gk20a *g, 0x419864, /* gr_pri_gpcs_tpcs_pe_l2_evict_policy */ 0x419a04, /* gr_pri_gpcs_tpcs_tex_lod_dbg */ 0x419a08, /* gr_pri_gpcs_tpcs_tex_samp_dbg */ + 0x419b48, /* gr_pri_gpcs_tpcs_sm_sch_macro_sched */ 0x419ba4, /* gr_pri_gpcs_tpcs_sm_disp_ctrl */ 0x419e84, /* gr_pri_gpcs_tpcs_sms_dbgr_control0 */ 0x419ea8, /* gr_pri_gpcs_tpcs_sms_hww_warp_esr_report_mask */ + 0x419eac, /* gr_pri_gpcs_tpcs_sms_hww_global_esr_report_mask */ }; size_t array_size; diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c index 9e35db32e..7b592b3bc 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c @@ -88,6 +88,7 @@ void gm20b_gr_init_get_access_map(struct gk20a *g, 0x418380, /* gr_pri_gpcs_rasterarb_line_class */ 0x418800, /* gr_pri_gpcs_setup_debug */ 0x418830, /* gr_pri_gpcs_setup_debug_z_gamut_offset */ + 0x4188b0, /* gr_pri_gpcs_mmu_debug_ctrl */ 0x4188fc, /* gr_pri_gpcs_zcull_ctx_debug */ 0x418e00, /* gr_pri_gpcs_swdx_config */ 0x418e40, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */ @@ -115,6 +116,9 @@ void gm20b_gr_init_get_access_map(struct gk20a *g, 0x419a04, /* gr_pri_gpcs_tpcs_tex_lod_dbg */ 0x419a08, /* gr_pri_gpcs_tpcs_tex_samp_dbg */ 0x419e10, /* gr_pri_gpcs_tpcs_sm_dbgr_control0 */ + 0x419e44, /* gr_pri_gpcs_tpcs_sms_hww_warp_esr_report_mask */ + 0x419e4c, /* gr_pri_gpcs_tpcs_sms_hww_global_esr_report_mask */ + 0x419eac, /* gr_pri_gpcs_tpcs_sm_sch_macro_sched */ 0x419f78, /* gr_pri_gpcs_tpcs_sm_disp_ctrl */ }; size_t array_size; diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c index 1ad9e2e41..4ceda1eae 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c @@ -60,6 +60,7 @@ void gv11b_gr_init_get_access_map(struct gk20a *g, 0x418380, /* gr_pri_gpcs_rasterarb_line_class */ 0x418800, /* gr_pri_gpcs_setup_debug */ 0x418830, /* gr_pri_gpcs_setup_debug_z_gamut_offset */ + 0x4188b0, /* gr_pri_gpcs_mmu_debug_ctrl */ 0x4188fc, /* gr_pri_gpcs_zcull_ctx_debug */ 0x418e00, /* gr_pri_gpcs_swdx_config */ 0x418e40, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */ @@ -86,9 +87,11 @@ void gv11b_gr_init_get_access_map(struct gk20a *g, 0x419864, /* gr_pri_gpcs_tpcs_pe_l2_evict_policy */ 0x419a04, /* gr_pri_gpcs_tpcs_tex_lod_dbg */ 0x419a08, /* gr_pri_gpcs_tpcs_tex_samp_dbg */ + 0x419b48, /* gr_pri_gpcs_tpcs_sm_sch_macro_sched */ 0x419ba4, /* gr_pri_gpcs_tpcs_sm_disp_ctrl */ 0x419e84, /* gr_pri_gpcs_tpcs_sms_dbgr_control0 */ 0x419ea8, /* gr_pri_gpcs_tpcs_sms_hww_warp_esr_report_mask */ + 0x419eac, /* gr_pri_gpcs_tpcs_sms_hww_global_esr_report_mask */ }; size_t array_size;